Survey: FPGA PCB layout

[Joerg]

Preferential? I think not. Civil service employees generally get
what was normal in industry 10 years ago. They usually trade job
security for about a sixth less pay. It is the near invulnerable job
security that is the problem.

But: John Doe does not get what was normal in industry 10 years ago. He
just gets ever increasing property tax and other bills. Followed by
eternal lamentations that those taxes aren't enough.

The litmus test is this: When an agency receives boatloads of
applications like it supposedly happens for the prison guard jobs then
something is seriously out of balance.

And yes, I agree with you that tenure track should not exist.

 

[Joerg]

Current pay rates are here:

http://www.dpa.ca.gov/publications/pay-scales/index.htm

Please note some of the wild variation in engineer classifications.
For this group we should look for electrical or electronic engineers.
Senior engineer supervises working engineers, supervising engineers
are the bosses of seniors, and they in turn report to principle
engineers.

I have not bothered to find historical pay rates yet. All of my peer
group has made more in private than in public positions. If you are
not doing as well, that is not my problem.

Research specialists making >10k/mo? That is a rather decent salary.
Most researchers in industry do not make that much.

Also, you have to consider that you guys have what almost amounts to
tenure. When the budget is tight the taxpayer is expected to jump in.
When the budget is tight in industry layoffs follow in due course. Right
now EE is on a roll but remember 2001-2004? How many folks with masters
degrees did low-wage jobs at hardware stores selling weed eaters and
circular saws? I've met some. That (usually) does not happen to people
in public service positions.

[...]

 

[Joerg]

Actually it never had it.

Although I must say that the folks who designed MS-Works did a fine job.
Even the Windows versions of it never crashed on me. That is quite
unusual for Windows programs.

 

[Joerg]

Yep. Volume issues. All the standard parts are RoHS. Then the
questions get asked. Fortunately there are recent 4-element alloys
that have fairly good properties and seem to lack tin whisker
problems. Nothing fully qualified for space / life critical quite
yet, but it is on the horizon.

I just hope RoHS doesn't blow up in our face like other hip-shot
decisions by politicos. Such as MTBE in California gasoline. But it
might. Only time will tell.

 

[krw]

Marion County, Florida recently laid off about half of it's building
inspectors and support staff. The trucks they drove were auctioned off
a few days ago, as well. That money will go back into the county's
general fund, as well as the unused salaries.

One of the local sheriffs just handed out pink slips to about half
his deputies and staff. He's looking for more tenants for his
hotel, to pay for those remaining. Maybe he should ask Joe Arpaio
for some help.

 

[[email protected]]

Yeah, after Dave posted that I checked and unfortunately Pulsonix can't do
it... although it's "close enough" that I imagine adding it as a feature
wouldn't be particularly difficult.  I think it's a good idea -- hopefully it
will show up in more tools over time.

There's a new tool on the market for this - Taray's 7 Circuits
http://www.tarayinc.com/
You do minimal floorplanning right in the tool, and it optimizes the I/
O assignment for the specific electrical characteristics of the
device, and the arrangements of the other major devices the FPGA is
connected to. Works with both Cadence and Mentor schematics. The nice
part is that the EE doesn't have to actually do any PCB layout, but it
makes the layout flow much better (fewer vias, layers, shorter
connections, etc).
-Brian