Simple pulse generator circuit

[Bill Sloman]

As I suggested, a couple of times, a dual one-shot (one chip) and a
NOR gate (one more) could do the job. One one-shot would be fixed at,
say, 100 ns, and the other would be adjusted from 110 to 260. The gate
takes the difference.

I could explain it in more detail if you don't get the concept.

It's not exactly a complicated idea. You wouldn't actually trim the
first one shot to 100nsec, you'd rely on the two one-shots on a single
substrate being more or less the same, and set up the first one for a
minimum pulse width - 2k to +5V and no capacitor - and set up the
second to cover the range from there - plus 10nnsec - out to about
300nsec.

I'd use a 74221, and program the pulse width on the second monostable
in the package with a current mirror delivering a constant but
adjustable (from about 2mA on down to perhaps 0.2mA or whatever - it's
a long time since I've done it) current into the Rext/Cext pin,
primarily to let me put the pot that programmed the pulse width a long
way from the 74221 generating the pulse without hanging a long aerial
on the Rext/Cext pin.

You could probably make the programming rheostat a 3-turn pot, with
each turn adding another 100nsec to the pulse width, and use an
auxiliary trim-pot to allow the range to start 10nsec. There'd
presumably be a op amp in there to convert the current being sunk into
the potentiometer into a current to be fed into the controlling side
of the current mirror.

There used to be application notes around that talked about doing
that, but I can't seem to find any of them

http://www2.elo.utfsm.cl/~lsb/elo211/datos/lacaja/74123.pdf

presents Nat. Semi.'s AN-366 from 1984, which is informative, but not
on that specific point.

http://www.fairchildsemi.com/an/AN/AN-138.pdf

shows the idea in action, but only on the CMOS version of the 221, and
there's no explanation of what's going on.

 

[Bill Sloman]

There is a potential output glitch hazard at the start, when both
one-shots are initially fired. That can be fixed by using a couple of
the other NOR sections to delay the start of the second (variable)
one-shot.

I'd be inclined to use the common input to both monostables to mask
the init

 

[Bill Sloman]

There is a potential output glitch hazard at the start, when both
one-shots are initially fired. That can be fixed by using a couple of
the other NOR sections to delay the start of the second (variable)
one-shot.

I'd probably use the common trigger to both monostables to mask the
output until one or other of them had fired; worst case 74221
propagation delay from trimmer to output is about 80nsec, which makes
the "best case" about 30nsec (but they don't specify it at all) and
the propagation delay through the gating logic should be long enough
to mask the glitch. It's the sort of thing you'd sort out at the
detail design level.

Or use the output of the first one-shot to fire the second one.

You might. It's a bit too crude and extravagant for anybody serious
about circuit design.

 

[[email protected]]

This is the way I generate precise delays (on-chip)...



http://www.analog-innovations.com/SED/DelayCircuitForNarrowPulseWidths.pdf



This delayed signal is then used to create non-overlapping drives for

such things as full-H bridges, and commutating switches used in

synchronous rectification and integrate control loops.



Analysis is left as an exercise for the student ;-)



Hints:



(1) These are 10ps inverters (TSMC 0.18u process)

(2) This is internal to a monolithic chip, so no ESD to get in your

way, so left end of the cap flys above VDDD and below GNDD without

clamping or consequence.



This snap-shot is from a chip I designed last fall when I did an

extended stay -) on Long Island and met Martin Riddle.



Designed entirely on my laptop, the chip worked perfectly to

specifications first pass thru the foundry, as do ALL of my designs...

I never do "designs" without component values >



...Jim Thompson

--

| James E.Thompson, CTO | mens |

| Analog Innovations, Inc. | et |

| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |

| Phoenix, Arizona 85048 Skype: Contacts Only | |

| Voice480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |



I love to cook with wine. Sometimes I even put it in the food.

That's a nice design variant on the multi-inverter oscillator, but I don't see where it lends itself to easy adjustability from a front panel mounted pot- or the equivalent located at some distance from the high speed components.
What the heck is wrong with a switched current source + capacitor ramp driving a high speed comparator, the other input of which is driven by a variable voltage threshold? The OP only wants a 25:1 pulse width adjustment so that's no big deal.

 

[Bill Sloman]

Extravagant? It avoids a race hazard by moving one wire; no additional
parts.

It introduces a good deal more delay than is strictly necessary. We've
already got the propagation delay from the initiating edge to the
output of the first monostable, and you want to add in the same
propagation delay for the second monostable? And a TTL monostable at
that, so the delay depends on the state of the 5V rail.

It's not crude, it's elegant.

Like everything else invented by John Larkin ...

I'm sure glad you don't work for me. Actually, I'm glad you don't work
for anybody.

Sure, I'm guilty of the unforgivable crime of not sharing your opinion
of John Larkin's virtues as a circuit designer. At least you won't be
tempted to report me to the FBI for harbouring dangerously anti-
American attitudes, as Jim Thompson says he did. There's no committee
- as yet - for investigating people who aren't sufficiently credulous
about John Larkin's self-advertising.

 

[Bill Sloman]

Of course you aren't dangerous. You aren't effective enough.

Don't tempt me. I only use my powers for good, but you do work for the
dark side from time to time, and not only by propagating climate
change denialist propaganda.

 

[[email protected]]

Dammit, stop making sense!

I'm with Jim on this one.



One shots in general are a bad idea. I went through great pains on a

multi-person design to use a counter to get around the one shot, only to

find in a power down mode the crystal was turned off. Fortunately, other

mistakes were in the chip so it wasn't like my screw up solely was to

blame for blowing up the design budget.



The trouble with one shots is they can be influenced by power supply

noise, temperature to some extend if gate delays are part of the

equation, etc. By the time you design a one shot as good as a Swiss

watch, it ends up being an analog beast.



This is the way I generate precise delays (on-chip)...



http://www.analog-innovations.com/SED/DelayCircuitForNarrowPulseWidths.pdf



This delayed signal is then used to create non-overlapping drives for

such things as full-H bridges, and commutating switches used in

synchronous rectification and integrate control loops.



Analysis is left as an exercise for the student ;-)



Hints:



(1) These are 10ps inverters (TSMC 0.18u process)

(2) This is internal to a monolithic chip, so no ESD to get in your

way, so left end of the cap flys above VDDD and below GNDD without

clamping or consequence.



This snap-shot is from a chip I designed last fall when I did an

extended stay -) on Long Island and met Martin Riddle.



Designed entirely on my laptop, the chip worked perfectly to

specifications first pass thru the foundry, as do ALL of my designs...

I never do "designs" without component values >



...Jim Thompson

[snip]

That's a nice design variant on the multi-inverter oscillator, but I don't see where it lends itself to easy adjustability from a front panel mounted pot- or the equivalent located at some distance from the high speed components.

In this case I didn't need adjustability. When I do, I generally do

an adjustment of the inverter rails... easy monolithically, tricky in

discrete's.

What the heck is wrong with a switched current source + capacitor ramp driving a high speed comparator, the other input of which is driven by a variable voltage threshold? The OP only wants a 25:1 pulse width adjustment so that's no big deal.

That works, but, down at 10ns that gets difficult at the discrete

device level.



Larkin promised us a schematic with component values, but never has

posted it.



You should adjust your wrap setting. I have mine set at 70 to allow

room for attribution marks without spillover.



...Jim Thompson

--

| James E.Thompson, CTO | mens |

| Analog Innovations, Inc. | et |

| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |

| Phoenix, Arizona 85048 Skype: Contacts Only | |

| Voice480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |



I love to cook with wine. Sometimes I even put it in the food.

OP:
That's a nice design variant on the multi-inverter oscillator, but I don't see where it lends itself to easy adjustability from a front panel mounted pot- or the equivalent located at some distance from the high speed components.
What the heck is wrong with a switched current source + capacitor ramp driving a high speed comparator, the other input of which is driven by a variable voltage threshold? The OP only wants a 25:1 pulse width adjustment so that's no big deal.
END OP

Did that wrap right?

 

[[email protected]]

I refused to help a

certain middle-eastern country develop nuclear weapons.

Haha-

 

[Bill Sloman]

Dark side? I refused to sell to tobacco companies. I refused to help a
certain middle-eastern country develop nuclear weapons. I've given
away far more than I've earned.

So where did you steal the unearned money that you have given away?
You've made it fairly clear that you didn't have an inherited fortune
to give away.

You don't use your powers for good; you aren't effective enough.

Not where you can see the effects.

So, do you admit that the dual one-shot thing has a race hazard?

Obviously - the propagation delay from the trigger to the start of the
output pulse can be anywhere from 20nsec to 70nsec for either
monostable, and you've got to mask that first 70nsec in consequence

If so, what's "too crude and extravagant" about my suggested fix? What do
you have that's better?

Anything with a shorter propagation delay; my preference was for a
short trigger pulse which could be used to mask the final output pulse
until both monostables could be relied on to have fired. I'm not going
to design the whole circuit just to prove the point - as far as I'm
concerned the two monostable solution is cheap and nasty, and I
wouldn't put in any effort on it until I was convinced that iCod
didn't need anything better

 

[Bill Sloman]

Haha-

They must have been desperately scraping the bottom of the barrel.

 

[Bill Sloman]

They wanted me to train their people in high-speed electronics design.
Good pay, travel, gratitude were offered.

So they couldn't afford Howard Johnson or Martin Graham, who don't
know much about high-speed electronic design either, but at least know
enough about training to write a - crummy - book.

It looks as if the nuclear holocaust is still some way off.

 

[Bill Sloman]

I haven't stolen anything. I offer products for sale, and sometimes
people buy them. I they're not happy, they can have their money back.



You're right about that.














So design something better. Post it here.

To what end? Would you admire the result, even if it were
breathtakingly perfect?

I prefer to waste my time amusing myself - it's playing to a more
critical audience.

In any event I'm off to Australia in a fortnight, and my wife wants me
to focus on getting packed up and organised.

 

[Bill Sloman]

What end? To design some real electronics.

I've done that, and wouldn't mind doing it again.

Meanwhile iCod hasn't actually told us enough about what he's doing
and what he wants his circuit to do to let us to design anything that
might qualify as "real" electronics.

At the moment you've got the hots for the 74123 when it's only worth
using instead of the 74121 when you need the re-trigger function,
which doesn't seem to be necessary in the application. We are a very
long way from "real" electronics.

 

[Bill Sloman]

I think your wife has chores scheduled for you anyhow.

I'm sure yours could find something more useful for you to do too.

 

[josephkk]

Dammit, stop making sense!
I'm with Jim on this one.
One shots in general are a bad idea. I went through great pains ona
multi-person design to use a counter to get around the one shot, only to
find in a power down mode the crystal was turned off. Fortunately,other
mistakes were in the chip so it wasn't like my screw up solely wasto
blame for blowing up the design budget.
The trouble with one shots is they can be influenced by power supply
noise, temperature to some extend if gate delays are part of the
equation, etc. By the time you design a one shot as good as a Swiss
watch, it ends up being an analog beast.
This is the way I generate precise delays (on-chip)...

http://www.analog-innovations.com/SED/DelayCircuitForNarrowPulseWidths.pdf

This delayed signal is then used to create non-overlapping drives for
such things as full-H bridges, and commutating switches used in
synchronous rectification and integrate control loops.
Analysis is left as an exercise for the student ;-)

Hints:

(1) These are 10ps inverters (TSMC 0.18u process)
(2) This is internal to a monolithic chip, so no ESD to get in your
way, so left end of the cap flys above VDDD and below GNDD without
clamping or consequence.
This snap-shot is from a chip I designed last fall when I did an
extended stay -) on Long Island and met Martin Riddle.
Designed entirely on my laptop, the chip worked perfectly to
specifications first pass thru the foundry, as do ALL of my designs...
I never do "designs" without component values >
...Jim Thompson
[snip]

That's a nice design variant on the multi-inverter oscillator, but I don't see where it lends itself to easy adjustability from a front panel mounted pot- or the equivalent located at some distance from the high speed components.

In this case I didn't need adjustability. When I do, I generally do

an adjustment of the inverter rails... easy monolithically, tricky in

discrete's.

What the heck is wrong with a switched current source + capacitor ramp driving a high speed comparator, the other input of which is driven by a variable voltage threshold? The OP only wants a 25:1 pulse width adjustment so that's no big deal.

That works, but, down at 10ns that gets difficult at the discrete

device level.



Larkin promised us a schematic with component values, but never has

posted it.



You should adjust your wrap setting. I have mine set at 70 to allow

room for attribution marks without spillover.



...Jim Thompson

--

| James E.Thompson, CTO | mens |

| Analog Innovations, Inc. | et |

| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |

| Phoenix, Arizona 85048 Skype: Contacts Only | |

| Voice480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |



I love to cook with wine. Sometimes I even put it in the food.

OP:
That's a nice design variant on the multi-inverter oscillator, but I don't see where it lends itself to easy adjustability from a front panel mounted pot- or the equivalent located at some distance from the high speed components.
What the heck is wrong with a switched current source + capacitor ramp driving a high speed comparator, the other input of which is driven by a variable voltage threshold? The OP only wants a 25:1 pulse width adjustment so that's no big deal.
END OP

Did that wrap right?

No. But thanks for trying.

?-)

 

[ehsjr]

No. But thanks for trying.

?-)

It wrapped correctly for me.

Ed