ring oscillator with stable frequency

[natali]

I'm trying to design a ring oscillator with stable frequency independent of change in supply voltage, temperature and process parameters using cadence. (0.18um technology node) 1.8v supply voltage. From the simulation of the circuit shown here, the frequency variation at the output is relatively large with respect to change in supply voltage. any suggestions please, to keep the frequency stable with change of supply voltage.

 

[duke37]

I see no frequency determining components.

 

[natali]

here is the simulation circuit

 

[LvW]

I see no frequency determining components.

For such an oscillator, the frequency is determined by the delay time between the stages.
Without any further elements the delay of each stage is set by the output resistance of the CMOS stage and the input capacitance of the next stage.
However, I suggest to use - at least - external grounded capacitors between the stages for defining the frequency. This would lower the sensitivity to supply voltage changes.
By the way: What is your frequency? Where are simulation results?

 

[natali]

For 1.8V we got frequency 0.67GHz.
For 1.6V we got 0.46GHz.
For 1.4V we got 0.28GHz.
So here while we change the Vdd from 1.8V to 1.4V there is a change in the O/p frequency.
are voltage regulators a possiblity to lower the sensitivity to supply voltages? and are there any other possibilities in the place of using the voltage regulator?

 

[LvW]

Do you need such large frequencies? Normally, an oscillator specification starts with the desired frequency.

 

[Arouse1973]

For such an oscillator, the frequency is determined by the delay time between the stages.
Without any further elements the delay of each stage is set by the output resistance of the CMOS stage and the input capacitance of the next stage.
However, I suggest to use - at least - external grounded capacitors between the stages for defining the frequency. This would lower the sensitivity to supply voltage changes.
By the way: What is your frequency? Where are simulation results?

Adding capacitors won't this also reduce the harmonic content and possibly produce a more sinusoidal wave shape?
Adam

 

[Arouse1973]

Another method that may work is to use large value resistor between the gates and the outputs this uses the resister and the very small gate capacitance to increase the propagation delay.
Adam

 

[hevans1944]

Is this circuit just part of the clock generator for a much larger digital integrated circuit design? Can you use an external resonator to set the frequency? BTW, what frequency are you trying to obtain? Relying on analog techniques to establish a clock frequency for a digital IC doesn't sound very state-of-the-art. And of course an on-chip regulator for the supply voltage will settle things down, at the expensive of more real estate and increased power dissipation. I bet there is some IP (intellectual property) out there somewhere to solve your problem.