Regarding I2C interface

[prav]

Hi all,

I have a basic question regarding I2C interface.

I have one master I2C ( some controller), which is used to configure
some configuration registers in 8 different chips.Now the problem is
these 8 differnt chips have an I2C interface(Slave only), all with the
same address.

My question is how will i configure the registers in 8 differnt chips
with different values simultaneously.

Any solution would be appreciated.

Thanks in advance,
Praveen

 

[PeteS]

Most devices designed to operate on an I2C interface have address pins.
Normally the address for I2C devices is made up of 4 class/device type
bits (bits 7-4), and 2 or 3 address input bits (bits 3-1 or 2-1, with
bit 3 fixed in the case of 2 address bits) and the read/write bit (bit
0) [The r/w bit is required to be bit 0 in the I2C spec].

If you only have two address bits, you are limited to 4 of that device
on one bus, unfortunately.

Are the devices you are using as slaves commercially available I2C
parts, or custom?

It's hard to know how to help without that information.

Cheers

PeteS

 

[Pooh Bear]

Hi all,

I have a basic question regarding I2C interface.

I have one master I2C ( some controller), which is used to configure
some configuration registers in 8 different chips.Now the problem is
these 8 differnt chips have an I2C interface(Slave only), all with the
same address.

My question is how will i configure the registers in 8 differnt chips
with different values simultaneously.

Any solution would be appreciated.

Ummm.....

Read the Philips spec would be a good start.

Btw - you can't update multiple registers * simultaniously * on I2C unless
I missed something.


Graham

 

[Anders F]

Hi all,

I have a basic question regarding I2C interface.

I have one master I2C ( some controller), which is used to configure
some configuration registers in 8 different chips.Now the problem is
these 8 differnt chips have an I2C interface(Slave only), all with the
same address.

My question is how will i configure the registers in 8 differnt chips
with different values simultaneously.

We take it you mean "from one master".

Any solution would be appreciated.

I second PeteS regarding the address pins and advice to use I2C multiplexers
the last bit of the way (or all the way if necessary)...

/A

 

[Rob Gaddi]

Hi all,

I have a basic question regarding I2C interface.

I have one master I2C ( some controller), which is used to configure
some configuration registers in 8 different chips.Now the problem is
these 8 differnt chips have an I2C interface(Slave only), all with the
same address.

My question is how will i configure the registers in 8 differnt chips
with different values simultaneously.

Any solution would be appreciated.

Thanks in advance,
Praveen

Short answer? You won't. If you've got all 8 chips on the same I2C
bus, with the same I2C address.....
a) Any attempt to write to any of them will write the same data to all
of them.
b) Any attempt to read from any of them will return nothing but garbled
nonsense.

I'd advise using either a bus switch such as the pca9548a or a bus
multiplexer like the pca9544a (you'll need two of them, they're only 4
line muxes) if you really need to have all 8 of them with the same slave
address. Actually, I'd really recommend finding a way to design this
such that you don't need to have 8 of the same device on the same slave
address, but that's just me.

 

[prav]

Hi,

My system looks like this.




--------------
I2C1 | |I2C5
Master1 ----------| |---------- to chip 1
| |I2C6
| |---------- to chip 2
| |I2C7
| |---------- to chip 3
I2C2 | |I2C8
Master2 ----------|Black box |---------- to chip 4
| |
| |I2C9
I2C3 | |---------- to chip 5
Master3 ----------| |I2C10
| |---------- to chip 6
| |I2C11
| |---------- to chip 7
I2C4 | |I2C12
Master4 ----------| |---------- to chip 8
| |
--------------


The information conveyed from the master is which chip to write to,and
also the address of the register along with the configuration
information to be written to the selected chip.
All the 8 chips work in slave mode only and all have the same I2C
address(i.e the reason we are going for 8 I2C buses and all the 8
chips are the same which are video decoder chips need to configure hue
, bightness and saturation etc of the video decoder chips , this
information is provided from the 4 different master ** Video Fixed
point Digital signal processor**).

Now my question is wether the blackbox shown can be implemented using
discrete chips(I2Cswitches/I2C mux) OR is it really feasible to
implement the black box in an FPGA.

Any solution would be appreciated.

Thanks in advance,
Praveen

 

[Pooh Bear]

Hi,

My system looks like this.




--------------
I2C1 | |I2C5
Master1 ----------| |---------- to chip 1
| |I2C6
| |---------- to chip 2
| |I2C7
| |---------- to chip 3
I2C2 | |I2C8
Master2 ----------|Black box |---------- to chip 4
| |
| |I2C9
I2C3 | |---------- to chip 5
Master3 ----------| |I2C10
| |---------- to chip 6
| |I2C11
| |---------- to chip 7
I2C4 | |I2C12
Master4 ----------| |---------- to chip 8
| |
--------------


The information conveyed from the master is which chip to write to,and
also the address of the register along with the configuration
information to be written to the selected chip.
All the 8 chips work in slave mode only and all have the same I2C
address(i.e the reason we are going for 8 I2C buses and all the 8
chips are the same which are video decoder chips need to configure hue
, bightness and saturation etc of the video decoder chips , this
information is provided from the 4 different master ** Video Fixed
point Digital signal processor**).

Now my question is wether the blackbox shown can be implemented using
discrete chips(I2Cswitches/I2C mux) OR is it really feasible to
implement the black box in an FPGA.

Any solution would be appreciated.

Thanks in advance,
Praveen

Sounds like you misunderstand how I2C works to be frank.

Why don't you address the I2C chips individually ?


Graham

 

[Robert Monsen]

Hi,

My system looks like this.




--------------
I2C1 | |I2C5
Master1 ----------| |---------- to chip 1
| |I2C6
| |---------- to chip 2
| |I2C7
| |---------- to chip 3
I2C2 | |I2C8
Master2 ----------|Black box |---------- to chip 4
| |
| |I2C9
I2C3 | |---------- to chip 5
Master3 ----------| |I2C10
| |---------- to chip 6
| |I2C11
| |---------- to chip 7
I2C4 | |I2C12
Master4 ----------| |---------- to chip 8
| |
--------------


The information conveyed from the master is which chip to write to,and
also the address of the register along with the configuration
information to be written to the selected chip.
All the 8 chips work in slave mode only and all have the same I2C
address(i.e the reason we are going for 8 I2C buses and all the 8
chips are the same which are video decoder chips need to configure hue
, bightness and saturation etc of the video decoder chips , this
information is provided from the 4 different master ** Video Fixed
point Digital signal processor**).

Now my question is wether the blackbox shown can be implemented using
discrete chips(I2Cswitches/I2C mux) OR is it really feasible to
implement the black box in an FPGA.

Any solution would be appreciated.

Thanks in advance,
Praveen

Unless there is something you aren't telling us, you can just hook the
chips up using a single two-wire bus; the masters will have to do
arbitration, but this is the kind of thing I2C is designed to do.

The I2C slaves are differentiated by setting a different address on
their address input lines. For example, the MCP23016 port expander from
microchip has 3 inputs that allow one to set the address it'll look for.
If I set it to 010 by tying the inputs to the proper voltages, for
example, it'll only accept commands on addresses 0100010 (7 bit
addressing).

The masters arbitrate by watching the output when the write data. If
another master is talking at the same time, one of their output bits is
going to be low when they stop driving it low. The winning master
doesn't even know it happened. Most hardware already does this. Doing it
in software is pretty easy too.

One issue with I2C is that the total capacitance on the bus must be less
than 400pF. The pullup resistors for the bus must be chosen so that the
bus comes up quickly enough. There are also schemes for increasing the
speed, which requires special hardware drivers.

The Phillips site has an I2C specification that describes the whole
thing, including fast transfer modes, and 10 bit addressing.

If you are determined to use a black box for some reason you can't tell
us, you can do this by with a microcontroller, FPGA, CPLD, etc. Using
discrete logic would be a nightmare. You would have to shift the address
bytes into a shift register, compare addresses, wait for the slave to be
free (since another master might already be using it), take control of
the proper bus, etc. However, since slaves can hold off masters
indefinitely, you could collect the address, hold off that master, write
the address out, and then simply open up a channel between them using an
analog switch.

--
Regards,
Robert Monsen

"Your Highness, I have no need of this hypothesis."
- Pierre Laplace (1749-1827), to Napoleon,
on why his works on celestial mechanics make no mention of God.

 

[Iwo Mergler]

Hi,

My system looks like this.

--------------
I2C1 | |I2C5
Master1 ----------| |---------- to chip 1
| |I2C6
| |---------- to chip 2
| |I2C7
| |---------- to chip 3
I2C2 | |I2C8
Master2 ----------|Black box |---------- to chip 4
| |
| |I2C9
I2C3 | |---------- to chip 5
Master3 ----------| |I2C10
| |---------- to chip 6
| |I2C11
| |---------- to chip 7
I2C4 | |I2C12
Master4 ----------| |---------- to chip 8
| |
--------------

The information conveyed from the master is which chip to write to,and
also the address of the register along with the configuration
information to be written to the selected chip.
All the 8 chips work in slave mode only and all have the same I2C
address(i.e the reason we are going for 8 I2C buses and all the 8
chips are the same which are video decoder chips need to configure hue
, bightness and saturation etc of the video decoder chips , this
information is provided from the 4 different master ** Video Fixed
point Digital signal processor**).

Now my question is wether the blackbox shown can be implemented using
discrete chips(I2Cswitches/I2C mux) OR is it really feasible to
implement the black box in an FPGA.

Any solution would be appreciated.

Thanks in advance,
Praveen

If you are serious about the simultaneous, your black box needs
to be a rather special set of I2C masters. To answer your question,
the only sane implementation would be in an FPGA.

If simultaneous is not important, an I2C GPIO extender and a set
of CMOS switches would do. Each master would write the "chip number"
into the IO extender followed by accessing the respective decoder
via its I2C address.

You'll have to make sure that no other master can get in between
the transfers.

Kind regards,

Iwo

 

[prav]

Hi all,

There is nothing confidential in the black box it is just a I2C
hub/switch.
The real scenario is that there are four Video Fixed point Digital
signal processor(masters) each has a I2C interface.Now these
processors will configure the brightness, hue , saturation etc of
TVP5150(video decoder),there are 16 such video decoder chips but i had
showed only 8 because The slave address select terminal (I2CSEL)
enables the use of two TVP5150A decoders tied to the same I2C bus.

I2CSEL WRITE ADDRESS
0 B8h
1 BAh

Now the problem is that any of the processor may configure registers
of any video decoder chip.
Any suggestions how to go about this design.
Wether we can do it using an FPGA(I2Chub) or can we go for any I2C
switch.

One more basic doubt i have is wether the I2C interface from the four
processors(masters) will be sitting on the same I2C bus, i.e only 2
pins OR 8 pins will come to the black box(FPGA OR I2c switch).

Any solution would be appreciated.

Thanks in advance,
Prav

 

[Rob Gaddi]

If you are serious about the simultaneous, your black box needs
to be a rather special set of I2C masters. To answer your question,
the only sane implementation would be in an FPGA.

If simultaneous is not important, an I2C GPIO extender and a set
of CMOS switches would do. Each master would write the "chip number"
into the IO extender followed by accessing the respective decoder
via its I2C address.

You'll have to make sure that no other master can get in between
the transfers.

Kind regards,

Iwo

FPGA is severe overkill, this is fairly doable off the shelf.

If only one of the masters is going to want to be writing to the
registers at any given time you can just put all four on the same I2C
bus, and connect that bus to either a 1-8 or pair of 1-4s as I said earlier.

Gets a little trickier if you want all of them to be able to play ball
at the same time. I'd say you can probably get away with four of those
pca9548a 1-8 I2C switches that I mentioned earlier. Use each to connect
1 master to all 8 slave buses, each of which has two slaves with
different addresses. You'll need to do some back of the envelope number
crunching with the data sheet to make sure that the extra capacitance of
three switches in the off position won't violate the aforementioned
400pf(?) limit, but it shouldn't.

This does however leave open the question of how to do bus collision
detection with the four masters. The I2C master hardware should do it
automatically, as Robert said, but caveat emptor on that point. If you
can spare 8 I/O lines on each of the masters you can just do an
open-drain wired OR where each line represents one slave bus. That way
if the I2C bus collision detection doesn't magically fall into place
you'll have your own side mechanism where you can set up as simple or as
complicated a collision avoidance as necessary. If you can't you could
always use an 8 bit GPIO extender on each master bus to implement the
same functionality, but that seems to be a bit much.

 

[Luhan Monat]

Hi all,

I have a basic question regarding I2C interface.

I have one master I2C ( some controller), which is used to configure
some configuration registers in 8 different chips.Now the problem is
these 8 differnt chips have an I2C interface(Slave only), all with the
same address.

My question is how will i configure the registers in 8 differnt chips
with different values simultaneously.

Any solution would be appreciated.

Thanks in advance,
Praveen

Use an external multiplexer on the clock line. Tie all the data lines
together. A 74hc138 can be addressed with 3 extra lines from the
processor. Use the Active Low '*E' input to run the clock to one of 8
I2C devices. Inactive outputs from the 138 are held high (as I recall).

 

[Robert Monsen]

Hi all,

There is nothing confidential in the black box it is just a I2C
hub/switch.
The real scenario is that there are four Video Fixed point Digital
signal processor(masters) each has a I2C interface.Now these
processors will configure the brightness, hue , saturation etc of
TVP5150(video decoder),there are 16 such video decoder chips but i had
showed only 8 because The slave address select terminal (I2CSEL)
enables the use of two TVP5150A decoders tied to the same I2C bus.

I2CSEL WRITE ADDRESS
0 B8h
1 BAh

Now the problem is that any of the processor may configure registers
of any video decoder chip.
Any suggestions how to go about this design.
Wether we can do it using an FPGA(I2Chub) or can we go for any I2C
switch.

One more basic doubt i have is wether the I2C interface from the four
processors(masters) will be sitting on the same I2C bus, i.e only 2
pins OR 8 pins will come to the black box(FPGA OR I2c switch).

Any solution would be appreciated.

Thanks in advance,
Prav

Ok, I looked up the thing, you only have two addresses to work with.

One hack would be to muck with the addresses... On the left side, with
the masters, you have a simple I2C slave, which listens for a set of
addresses. Once an address is decoded, you hold off the master using
SCL, and use the address input to the video decoder as a chip select.
Everybody with a low bit expects the address to be B8. The one guy with
a 1 expects the address to be BA. You then output BA as the command on
the slave I2C bus as master. Once it's out on the bus, you just start
mapping everything one to one...

Then, all of the slaves can be on a single I2C bus, and all of the
masters can also be on their own I2C bus. This may be simpler, assuming
the I2CSEL pin can be modified on the fly.

--
Regards,
Robert Monsen

"Your Highness, I have no need of this hypothesis."
- Pierre Laplace (1749-1827), to Napoleon,
on why his works on celestial mechanics make no mention of God.

 

[prav]

rob,
You are telling me to connect all the four masters on to a single I2C
bus , but it is not possible in our system, since all the masters have
the same address.
one more assumption is there will not be any overlap i.e there will
not be any case where the two masters are trying to access the same
chip.Hence no arbitartion required.

In my understanding i need four I2C slaves in the FPGA which talk to
the for masters,and i need 8 I2C masters which talk to 8 I2C slave
chips.
Some glue logic is required b/w these 4 slaves and 8 masters in FPGA.

Any suggestions would be appreciated.

Thanks in advance,
Praveen

 

[Iwo Mergler]

rob,
You are telling me to connect all the four masters on to a single I2C
bus , but it is not possible in our system, since all the masters have
the same address.

Masters don't have addresses, only slaves have. Bus arbitration
between masters is done over the slave address + data.

Your master devices may have slave ports, but unless you're actually
addressing them, you don't need to worry about it.

I would suggest you read and understand this document:

http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf

one more assumption is there will not be any overlap i.e there will
not be any case where the two masters are trying to access the same
chip.Hence no arbitartion required.

In my understanding i need four I2C slaves in the FPGA which talk to
the for masters,and i need 8 I2C masters which talk to 8 I2C slave
chips.
Some glue logic is required b/w these 4 slaves and 8 masters in FPGA.

Yes, this is the overkill Rob talked about. The only reason for doing
this kind of stuff is if you need to preload some register settings and
then dump them *simultaneously* (= at exactly the same time)
into the slaves.

If you truly need to do this, the FPGA is required, but you can optimise
a little. You would need a (single) special slave in the FPGA, one which
responds to, say 16 I2C addresses. The 4 address bits give you the target
information.

The 8 master blocks could be relatively simple, as they don't have to
support arbitration.

Then you would need to think about how to synchronise the transfers
and read back the acknowledge status.

Kind regards,

Iwo

 

[prav]

Hi rob ,

As suggested by u i went through the I2C spec.
In the spec , page 17, Fig 16 gives the format for
Data transfer from a hardware master-transmitter.
which shows that there is a master address.

But u had said that masters do not have any address, only slaves have.

Please clarify

Thanks in advance,
Praveen

rob,
You are telling me to connect all the four masters on to a single I2C
bus , but it is not possible in our system, since all the masters have
the same address.

Masters don't have addresses, only slaves have. Bus arbitration
between masters is done over the slave address + data.

Your master devices may have slave ports, but unless you're actually
addressing them, you don't need to worry about it.

I would suggest you read and understand this document:

http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf

 

[Iwo Mergler]

Hi rob ,

As suggested by u i went through the I2C spec.
In the spec , page 17, Fig 16 gives the format for
Data transfer from a hardware master-transmitter.
which shows that there is a master address.

But u had said that masters do not have any address, only slaves have.

Please clarify

Thanks in advance,
Praveen

It's the CBUS protocol, which was designed to live alongside
I2C.

It's based on the idea of using an otherwise unallocated
I2C slave address to encapsulate a different protocol.

CBUS does have the concept of a master address. In that respect,
it is similar to CAN, the masters say who they are and the slaves
listen to whatever masters they want.

In your case, I don't think any of your devices speaks CBUS,
so the above is probably quite irrelevant.

Kind regards,

Iwo