Question regarding FET with low Drain to Source capacitance - FET_termination.jpg (0/1)

[LRCR]

Fred,

Thank you for your response. In my setup, I use a video generator
that is capable sweeping from 1 MHz to 30MHz with an amplitude of
100IRE or 714mV. I view the sweep on a oscilloscpe and observe the
amplitude attenuation. In the case of this MOSFET design, the
attenuation of the signal goes down -3dB(Approx. 0.5v from 714mV) at
15.4MHz. Since the signal is so small across FET's drain to source
ends, it is possible that the capacitance can be high per the data
sheet. In fact where I am at on the drain to source, Coss is 75pF,
Ciss is 50pF and Crss is 30pF. The capacitance across G-D, G-S and
D-S are:

Cgd = Crss = 50pF
Cgs = Ciss -Crss = 20pF
Cds = Coss - Crss = 45pF

Miller Cmout= Cgd(Av+1)/Av = 60pF with Av=1

Miller Cmin = 0 and Cgs = 0 since the source is gnd as the gate is
also ground.

Therefore,

Capacitance across the circuit where the FET's Drain to Source is
connected to:

Total Capacitance = Cmout+Cds +Cgs = 60pF+45pF+30pF = 135pF

Pretty close to what I measured, 137PF. Honestly, I was surprise with
this large number. From all the feedback I got from everyone and my
measurements, it seems that the Bipolar approach may be a better
choice. Also, from one of the feedback, John, I am also concerned
with the DC drift on the video signal that I also observed on the
video analyzer, VM700.

If you disagree with these findings, please send me your feedback
since it helps me to understandand find a proper solution to this
design.

Thanks
Caesar

 

[LRCR]

Thanks Win for you reply,

I will look into your suggession regarding using a MOSFET with CMOS
and " bipolar photoMOS optocoupler relay switches".

Thanks
Caesar

 

[Fred Bloggs]

Fred,

Thank you for your response. In my setup, I use a video generator
that is capable sweeping from 1 MHz to 30MHz with an amplitude of
100IRE or 714mV. I view the sweep on a oscilloscpe and observe the
amplitude attenuation. In the case of this MOSFET design, the
attenuation of the signal goes down -3dB(Approx. 0.5v from 714mV) at
15.4MHz. Since the signal is so small across FET's drain to source
ends, it is possible that the capacitance can be high per the data
sheet. In fact where I am at on the drain to source, Coss is 75pF,
Ciss is 50pF and Crss is 30pF. The capacitance across G-D, G-S and
D-S are:

Cgd = Crss = 50pF Cgs = Ciss -Crss = 20pF Cds = Coss - Crss = 45pF

Miller Cmout= Cgd(Av+1)/Av = 60pF with Av=1

Miller Cmin = 0 and Cgs = 0 since the source is gnd as the gate is
also ground.

Therefore,

Capacitance across the circuit where the FET's Drain to Source is
connected to:

Total Capacitance = Cmout+Cds +Cgs = 60pF+45pF+30pF = 135pF

Pretty close to what I measured, 137PF. Honestly, I was surprise
with this large number. From all the feedback I got from everyone
and my measurements, it seems that the Bipolar approach may be a
better choice. Also, from one of the feedback, John, I am also
concerned with the DC drift on the video signal that I also observed
on the video analyzer, VM700.

If you disagree with these findings, please send me your feedback
since it helps me to understandand find a proper solution to this
design.

Thanks Caesar

That Aromat AQY221 in WH's post looks like just the thing- and fully
characterized to 10MHz- looks to have slow rolloff beyond that.

 

[LRCR]

Thanks Fred. I will check on this part.

Caesar