PWM Amp Design

[Chris Carlen]

Greetings:

I'm designing a PWM amp PCB module based on the Apex Microtechnology
SA60 chip. Target specs are to be able to sustain 80V at up to 7.1A
continuously and 10A max. into a load of unspecified resistance. That
means for small load resistances, the output voltage might not ever
reach 80V, but for any load resistance, the output current must be able
to reach 7.1A continuously. Frequency response should be flat to -3dB
at 10kHz or better.

The PWM amp is closed loop with a differential output voltage sense amp
feeding into a simple integrating summing amp driving the PWM control
input, which also has the main input signal applied. Note that the
output voltage sense is done prior to output filtering, so that a simple
integrator compensation is able to maintain control.

The output is filtered with a differential LC Butterworth arrangement,
the LC values of course needing to be tuned to the load resistance. I
have chosen a 125kHz switching frequency. The output filter cutoff will
be 12.5kHz.

My present load will be a 2.5 ohm coil with 250uH of inductance. Thus
the LC filter elements are 22.5uH and 7.2uF.

The inductive load requires equalization to cancel its reactance or else
the LC filter for the PWM becomes resonant with the added load
inductance, resulting in freq. response peaking. To fix this, I have
added a 2.5ohm resistor in series with a 40uF capacitor across the load.

This all works fine except for some drawbacks. Obviously, at high
frequencies near and above the crossover frequency of the load RL
combination, the equalizer RC network begins to conduct substantial
current and dissipating massive power. Up to about 115W at the output
specs mentioned.

I should point out that the application signal has an upper bandwidth of
only about 150Hz, so the 10kHz amplifier response is way overkill. The
point is that at 150Hz, I want very low phase shift for a servo loop, so
the wide band amp relative to the application is warranted. (Actually,
perhaps only about 3kHz might suffice).

However, for more academic purposes I am still curious about what other
approaches other than an equalizing network one might try to solve the
reactance problem? It seems to me that one approach might be to try to
sense the PWM output post-filter, and then compensate for the peaking
within the PWM amplifier control loop.

Is this typically done?

I am as of yet unable to do this, because my AC model for the PWM amp
power train is inadequate. I am aware of the state space averaging and
other models which correctly predict the presence of a right plane zero
in these circuits. I think I need to be able to understand this and be
able to compute the correct model for my PWM amp before I can attempt
designing the correct loop compensation.

One possible advantage of post-filter PWM amp output voltage sensing and
control might be to eliminate the overshoot inherent in the output
filter (or I suppose the filter might be damped down to a Bessel
response as well).

It seems problematic that the output filters for a PWM amp must be tuned
to the load impedance, and if there is substantial load reactance, that
additional compensating measures must be taken which either waste power
or complicate the compensation required.

Maybe linear amplifiers are not so bad after all. I tend to prefer them
since they are ripple free, but in this case I opted for the PWM amp
because 4 channels must fit along with 1200W of power supplies, and
bunch of other CPU type electronics in a 7" high rack chassis. That
just didn't seem feasible or power efficient with linear amps.


Thanks for your comments.


Good day!


--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

 

[Larry Brasfield]

Greetings: Salutation.
I'm designing a PWM amp PCB module based on the Apex Microtechnology SA60 chip.

(A note for other readers: That is an H-bridge MOSFET switch
without internal feedback and a near-linear optional sawtooth
generator to help convert an input to PWM.)

Target specs are to be able to sustain 80V at up to 7.1A continuously and 10A max. into a load of unspecified resistance.

Specifying at least a range would help a lot. Does the
load actually change once a system is built? Or do
you just not know the load yet?

That means for small load resistances, the output voltage might not ever reach 80V, but for any load resistance, the output
current must be able to reach 7.1A continuously.

Is current limiting an issue? (I would think so if the
load is as ill-behaved as you have allowed here.)

Frequency response should be flat to -3dB at 10kHz or better.

If phase delay up to 150 Hz is what you really care about,
it would be more useful to know that requirement.

The PWM amp is closed loop with a differential output voltage sense amp feeding into a simple integrating summing amp driving the
PWM control input, which also has the main input signal applied. Note that the output voltage sense is done prior to output
filtering, so that a simple integrator compensation is able to maintain control.

I suggest that, with an appropriate controller, it would
be fine to control the filter output instead. That would
likely simplify getting the phase delay you want, by
easing the derived and hence subsidiary requirements.

The output is filtered with a differential LC Butterworth arrangement, the LC values of course needing to be tuned to the load
resistance.

That makes me think the load may be knowable after all.

I have chosen a 125kHz switching frequency. The output filter cutoff will be 12.5kHz.

Is it a 2 pole LC LPF, nominally?

My present load will be a 2.5 ohm coil with 250uH of inductance. Thus the LC filter elements are 22.5uH and 7.2uF.

Is there any reason you cannot adjust the controller
response to accomodate the load variation?

The inductive load requires equalization to cancel its reactance or else the LC filter for the PWM becomes resonant with the added
load inductance, resulting in freq. response peaking.

The controller could provide the damping without
the necessity of dissipation or extra HF output.

To fix this, I have added a 2.5ohm resistor in series with a 40uF capacitor across the load.

That is a hit with respect to ripple.

This all works fine except for some drawbacks. Obviously, at high frequencies near and above the crossover frequency of the load
RL combination, the equalizer RC network begins to conduct substantial current and dissipating massive power. Up to about 115W at
the output specs mentioned.

EMI might suffer, too, depending on what the
inductors really look like.

I should point out that the application signal has an upper bandwidth of only about 150Hz, so the 10kHz amplifier response is way
overkill. The point is that at 150Hz, I want very low phase shift for a servo loop, so the wide band amp relative to the
application is warranted. (Actually, perhaps only about 3kHz might suffice).

With a controller designed to bring the LC LPF
poles where they would help form a traditionally
design, controlled phase-delay filter, I expect the
difference between your desired passband and
the switching frequency will make it an easy job.

However, for more academic purposes I am still curious about what other approaches other than an equalizing network one might try
to solve the reactance problem? It seems to me that one approach might be to try to sense the PWM output post-filter, and then
compensate for the peaking within the PWM amplifier control loop.

Glad you are open to this.

Is this typically done?

I don't know about typical. I've done exactly that
for a system with much less separation between the
intended signal band and the switching frequency.

I am as of yet unable to do this, because my AC model for the PWM amp power train is inadequate. I am aware of the state space
averaging and other models which correctly predict the presence of a right plane zero in these circuits.

The simple PWM with bridge does not have the RHP
zero and its response is quite consistent as long as the
initial filter inductors do saturate and the input supply
is relatively stable.

I think I need to be able to understand this and be able to compute the correct model for my PWM amp before I can attempt
designing the correct loop compensation.

The response is very simple. The transfer function
is a constant once the switching frequency is taken
out. Write a few expressions for the steady state
DC output versus duty cycle and see for yourself.

One possible advantage of post-filter PWM amp output voltage sensing and control might be to eliminate the overshoot inherent in
the output filter (or I suppose the filter might be damped down to a Bessel response as well).
Yes.

It seems problematic that the output filters for a PWM amp must be tuned to the load impedance, and if there is substantial load
reactance, that additional compensating measures must be taken which either waste power or complicate the compensation required.

That would depend on how far the poles are moved
by the controller relative to the variation in their open
loop positions due to load variation. I do not see an
inherent problem, depending on your final accuracy
requirements.

Maybe linear amplifiers are not so bad after all. I tend to prefer them since they are ripple free, but in this case I opted for
the PWM amp because 4 channels must fit along with 1200W of power supplies, and bunch of other CPU type electronics in a 7" high
rack chassis. That just didn't seem feasible or power efficient with linear amps.

Given your requirements, PWM with appropriate
feedback and control seems like a good choice.

Thanks for your comments.

You're most welcome.

 

[Chris Carlen]

Specifying at least a range would help a lot. Does the load actually
change once a system is built? Or do you just not know the load yet?

My idea was that since I had to build an amp for about 3.5A RMS into the
load of 2.5ohm+250uH for a specific application in which the load will
never change, that I might use the opportunity to make a somewhat more
generalized hardware foundation which could be used for similar
applications in the future with different loads. Hence the
"unspecified" load. Reasonably speaking, we would be considering mostly
slightly inductive loads such as motors and solenoids ranging from
perhaps 0.5-20ohms, and 10-1000uH. I doubled the current capability
from my application's 3.5A RMS (but must be able to deliver 10A peak
currents anyway, so the filter inductors mustn't go flat at that
current) to 7A just for flexibility.

Is current limiting an issue? (I would think so if the load is as
ill-behaved as you have allowed here.)

At this point, current limit isn't necessary. I don't like being
unprotected from short circuit, but the complexity of implementing this
vs. the timeframe for getting something running (this is an experimental
lab apparatus application, not a commercial product) forces me to
implement the simplest approach first. I can spend time on refinements
later.

Current limiting would also be complicated by the fact that we need to
be able to deliver accelerating currents of 10A to perhaps even the
SA60's 15A peak capability, which the load coils can handle briefly, but
not continuously. So a current limit designed to protect the load would
have to allow short bursts of high current, but somehow take into
account the average power limitations of the load as well as its
transient thermal limitations.

If phase delay up to 150 Hz is what you really care about, it would
be more useful to know that requirement.

2 degrees.

I suggest that, with an appropriate controller, it would be fine to
control the filter output instead. That would likely simplify
getting the phase delay you want, by easing the derived and hence
subsidiary requirements.


That makes me think the load may be knowable after all.


Is it a 2 pole LC LPF, nominally?
Yes.


Is there any reason you cannot adjust the controller response to
accomodate the load variation?

There is no load variation in this case. The response would have to be
adjusted for different load applications.

The controller could provide the damping without the necessity of
dissipation or extra HF output.

That would be cool (in more ways than one.)

That is a hit with respect to ripple.

Huh? Wouldn't crossover of load current at high frequency to the
capacitive branch actually reduce ripple? Oh wait, or does it modify
the filter response so as to reduce the cutoff slope? No! That's the
point of the equalization, to present to the filter an effective
resistive load of 2.5 ohms at all frequencies. But from the real load's
perspective...it sees its current dropping off as its own inductance
kicks in. Actually, since the voltage across both the real load and the
capacitive branch are the same, I don't think there is any effect on
ripple. I'll have to check this.

EMI might suffer, too, depending on what the inductors really look
like.

Do you mean because they are having to conduct the full current expected
from a resistive load at the cutoff freq. whereas if there was no
capacitive equalizer, then their current thus radiated mag. field would
drop off more quickly at HF?

With a controller designed to bring the LC LPF poles where they would
help form a traditionally design, controlled phase-delay filter, I
expect the difference between your desired passband and the switching
frequency will make it an easy job.
Hmm.


Glad you are open to this.


I don't know about typical. I've done exactly that for a system with
much less separation between the intended signal band and the
switching frequency.

That's a good sign.

The simple PWM with bridge does not have the RHP zero and its
response is quite consistent as long as the initial filter inductors
do saturate and the input supply is relatively stable.

Saturate? Why would we want that? Perhaps you mean "don't saturate?"

They will be designed to hold up at least 75% of their inductance to 10A.

The response is very simple. The transfer function is a constant
once the switching frequency is taken out. Write a few expressions
for the steady state DC output versus duty cycle and see for
yourself.

Yes, I have already done this. Quite a while ago I did a sim where it
seemed things *didn't* work with this model, but did work in reality.
Kind of backwards from what usually happens. I thought because my AC
model was missing the RHP. Perhaps you are correct. Now the other day
I discovered that maybe my model wasn't so broke after all. I haven't
pursued it very thoroughly because I knew I could get away with a simple
integrator and "turn the knobs until it works" design based on the
simple topology in Apex's app note AN33. But I hate to design things
that way. Like I said, we need a result and I have already gotten
burned once in this project for spending too much time making sure
things worked theoretically, while some other guy just empirically
tinkered his way to a working result (that's referring to the outer
control loop in which this amplifier will fit).

That would depend on how far the poles are moved by the controller
relative to the variation in their open loop positions due to load
variation. I do not see an inherent problem, depending on your final
accuracy requirements.

I need to spend some more time with pencil and paper to understand how
the controller can "move the poles" of the filter. I think you mean
that the closed loop transfer function will have it's poles not in the
same place as the open loop right? So far I haven't dealt with any
cases of having complex poles in the open loop, so this is virgin territory.

Given your requirements, PWM with appropriate feedback and control
seems like a good choice.

Yes, a linear amp would have needed water cooling to fit in the desired
package.

Thanks for the input.

Good day!

 

[Larry Brasfield]

My idea was that since I had to build an amp for about 3.5A RMS into the load of 2.5ohm+250uH for a specific application in which
the load will never change, that I might use the opportunity to make a somewhat more generalized hardware foundation which could
be used for similar applications in the future with different loads. Hence the "unspecified" load. Reasonably speaking, we would
be considering mostly slightly inductive loads such as motors and solenoids ranging from perhaps 0.5-20ohms, and 10-1000uH. I
doubled the current capability from my application's 3.5A RMS (but must be able to deliver 10A peak currents anyway, so the filter
inductors mustn't go flat at that current) to 7A just for flexibility.

Great. That makes the controller design a lot
easier since it can be revised (but only slightly)
for subsequent applications.

At this point, current limit isn't necessary. I don't like being unprotected from short circuit, but the complexity of
implementing this vs. the timeframe for getting something running (this is an experimental lab apparatus application, not a
commercial product) forces me to implement the simplest approach first. I can spend time on refinements later.

I would think it could be added later without much
interaction with the basic system. (There could be
control issues, of course, in whatever outer loop
this PWM+mover ends up in.)

Current limiting would also be complicated by the fact that we need to be able to deliver accelerating currents of 10A to perhaps
even the SA60's 15A peak capability, which the load coils can handle briefly, but not continuously. So a current limit designed
to protect the load would have to allow short bursts of high current, but somehow take into account the average power limitations
of the load as well as its transient thermal limitations.


2 degrees.

I suppose I can translate that to flat delay within +/- 37 uS
from DC to 150 Hz and beyond that, don't care.

Yes.

That, too, simplifies the controller and the math
(if any) behind it.

There is no load variation in this case. The response would have to be adjusted for different load applications.

May I presume you are willing to use a 10% ceramic
cap and 5% gapped core set for the inductor? (This
may well be relaxed once the phase delay performance
is simulated or analyzed with respect to sensitivity.)

That would be cool (in more ways than one.)

I've always liked electronic damping.

Huh? Wouldn't crossover of load current at high frequency to the capacitive branch actually reduce ripple? Oh wait, or does it
modify the filter response so as to reduce the cutoff slope? No! That's the point of the equalization, to present to the filter
an effective resistive load of 2.5 ohms at all frequencies. But from the real load's perspective...it sees its current dropping
off as its own inductance kicks in. Actually, since the voltage across both the real load and the capacitive branch are the same,
I don't think there is any effect on ripple. I'll have to check this.

Perhaps I misread your statement. I took it as
(a 2.5ohm resistor in series with a 40uF capacitor)
across the load
whereas you apparently meant
a 2.5ohm resistor in series with (a 40uF capacitor
across the load).
At any rate, I would get rid of the resistor, except for
a residual to be used for current sensing later.

Do you mean because they are having to conduct the full current expected from a resistive load at the cutoff freq. whereas if
there was no capacitive equalizer, then their current thus radiated mag. field would drop off more quickly at HF?

I mean because of my misunderstanding of your network.

Hmm.

Having sketched a quick root-locus for this, I
am still convinced. I have two complex poles
in G, near the imaginary axis, and two zeros in
H near the real axis and about as far from the
origin as the LPF poles. (And some poles way
to the left to make it realizable.) With the right
loop gain, the poles move to the left and around
the zero pair, ending up just about wherever they
are most useful for that controlled delay filter I
mentioned.

What kind of DC accuracy do you need? Can
gain variation induced by 80V supply variation
be handled by an outer loop? Or does this power
amp have to have very tight gain and offset specs?
(Until it appears necessary, I hesitate to add a pole
at zero just to reduce maybe tolerable error.)

That's a good sign.

That was a bit of a challenge, but your task is
enough easier that I wanted to offer that
encouragement.

Saturate? Why would we want that? Perhaps you mean "don't saturate?"

Yes. (I don't know why proof-reading is so hard.)

They will be designed to hold up at least 75% of their inductance to 10A.

Gapped parts would do better. If the open-loop
response can be kept more predictable, it will be
easier to control the close-loop phase delay. The
LC poles do not have to be kept so far out.

I should have said "for the quasi-steady-state from
one cycle to another". The DC case is trivial and
not of much use for a transfer function. The method
I prefer, for fixed switching frequency, is to analyze
cycle to cycle increments as a function of duty cycle
and translate those to equivalent derivatives.

Yes, I have already done this. Quite a while ago I did a sim where it seemed things *didn't* work with this model, but did work
in reality. Kind of backwards from what usually happens. I thought because my AC model was missing the RHP. Perhaps you are
correct.

As long as the H-bridge switches are always on, either
one way or the other, (and the inductor is constant!),
it really is that simple. You can think of the bridge as
simply a "DC" signal with some AC on it. (There is also
a delay, on the order of a partial cycle, but that can be
ignored when you are willing to filter off the AC anyway.)
The "DC" part is just the mean as affected by duty cycle.

Now the other day I discovered that maybe my model wasn't so broke after all. I haven't pursued it very thoroughly because I knew
I could get away with a simple integrator and "turn the knobs until it works" design based on the simple topology in Apex's app
note AN33.

Two poles near the imaginary axis plus one at
0 is a formula for something that either oscillates
or is very poorly damped.

But I hate to design things that way. Like I said, we need a result and I have already gotten burned once in this project for
spending too much time making sure things worked theoretically, while some other guy just empirically tinkered his way to a
working result (that's referring to the outer control loop in which this amplifier will fit).

I'd like to see him empirically stabilize a rocket.
(But from quite a distance.)

I need to spend some more time with pencil and paper to understand how the controller can "move the poles" of the filter. I think
you mean that the closed loop transfer function will have it's poles not in the same place as the open loop right?

Yes. As long as there is some loop gain, the poles
are shifted from their open-loop positions.

So far I haven't dealt with any cases of having complex poles in the open loop, so this is virgin territory.

That's were it becomes fun. With a few more
answers, I am inclined to simulate a controller
and idealization of your plant.

Yes, a linear amp would have needed water cooling to fit in the desired package.

Thanks for the input.

Good day!

You're welcome, and likewise.

 

[Nico Coesel]

Greetings:

I'm designing a PWM amp PCB module based on the Apex Microtechnology
SA60 chip. Target specs are to be able to sustain 80V at up to 7.1A
continuously and 10A max. into a load of unspecified resistance. That
means for small load resistances, the output voltage might not ever
reach 80V, but for any load resistance, the output current must be able
to reach 7.1A continuously. Frequency response should be flat to -3dB
at 10kHz or better.

The PWM amp is closed loop with a differential output voltage sense amp
feeding into a simple integrating summing amp driving the PWM control
input, which also has the main input signal applied. Note that the
output voltage sense is done prior to output filtering, so that a simple
integrator compensation is able to maintain control.

The output is filtered with a differential LC Butterworth arrangement,
the LC values of course needing to be tuned to the load resistance. I
have chosen a 125kHz switching frequency. The output filter cutoff will
be 12.5kHz.

This all works fine except for some drawbacks. Obviously, at high
frequencies near and above the crossover frequency of the load RL
combination, the equalizer RC network begins to conduct substantial
current and dissipating massive power. Up to about 115W at the output
specs mentioned.

Sounds like something I designed a few years back (with less power
output though) for an induction loop amplifier. The compensation
filter is a pain in the ass where it comes to dissipation.

Did you look into:
http://www.semiconductors.philips.com/acrobat_download/datasheets/TDA8924_1.pdf

This device seems a lot more rugged and complete than the SA60 chip.
Despite the lesser specs, I think it will still do well for the
project you're working on.
One of the advantages is that the TDA8924 can work with much higher
frequencies which makes the output filter easier to build (as you can
see from the sample diagram).
If EMI is a concern, you can use a common mode filter between the
output and the load.

 

[John Woodgate]

I read in sci.electronics.design that Nico Coesel <[email protected]>
wrote (in <[email protected]>) about 'PWM Amp Design',

Sounds like something I designed a few years back (with less power
output though) for an induction loop amplifier. The compensation filter
is a pain in the ass where it comes to dissipation.

You put a Zobel network (series RC) across the loop? There is a much
better solution described in BS 7594, using a series capacitor and one
or two resistors. But these days, there is usually no reason not to use
a current-drive amplifier.

 

[Nico Coesel]

I read in sci.electronics.design that Nico Coesel <[email protected]>
wrote (in <[email protected]>) about 'PWM Amp Design',


You put a Zobel network (series RC) across the loop? There is a much
better solution described in BS 7594, using a series capacitor and one
or two resistors. But these days, there is usually no reason not to use
a current-drive amplifier.

I used a Zobel network indeed (I more or less followed the HIP4080
appnote). But when it comes to class D amplifiers I came to the
conclusion that trying to make a perfect filter network using bessel
or butterworth is a futile excercise. The inductor and capacitor
values will vary too much because of the changing currents and
voltages.

Also, a zobel filter depends highly on the load, so you would need to
fit a different filter for every application or make it adjustable.
In case of a induction loop amplifier, the number of tables and chairs
and their location in the room would enter the equation )

In other words, butterworth, bessel and zobel look nice in theory, but
their practical use is very limited when it comes to class D
amplifiers.

I found out that using some inductors and capacitors to smear the
pulses into something that looks like a signal and using a common mode
filter as a final stage to get rid of the HF components works much
better.

 

[Larry Brasfield]

in message news:[email protected]... ....

....

[re phase delay up to 150 Hz]

I suppose I can translate that to flat delay within +/- 37 uS
from DC to 150 Hz and beyond that, don't care. .... ....
May I presume you are willing to use a 10% ceramic
cap and 5% gapped core set for the inductor? (This
may well be relaxed once the phase delay performance
is simulated or analyzed with respect to sensitivity.)

The design is not very sensitive considering the fairly
wide group delay band that is apparently allowed.
The above accuracy is likely to be excessive.

....

Having sketched a quick root-locus for this, I
am still convinced. I have two complex poles
in G, near the imaginary axis, and two zeros in
H near the real axis and about as far from the
origin as the LPF poles. (And some poles way
to the left to make it realizable.) With the right
loop gain, the poles move to the left and around
the zero pair, ending up just about wherever they
are most useful for that controlled delay filter I
mentioned.

What kind of DC accuracy do you need? Can
gain variation induced by 80V supply variation
be handled by an outer loop? Or does this power
amp have to have very tight gain and offset specs?
(Until it appears necessary, I hesitate to add a pole
at zero just to reduce maybe tolerable error.)

Upon further reflection, an integrator in the forward
path to get precise gain and offset is no big deal.
With a little tweaking to get the 3 poles properly
related to each other, the group delay easily falls
within a couple uS band out to 400 Hz. With even
more effort, (ajusting the zero positions and care
in setting loop gain), the 3 poles could be made to
conform to a cookbook equiripple group delay LPF.
From the initial results of simulation, I see no need
to bother with that mathematical exercise.

....

Gapped parts would do better. If the open-loop
response can be kept more predictable, it will be
easier to control the close-loop phase delay. The
LC poles do not have to be kept so far out.

For the simulation included below, I set the LC poles
about 10 times closer to the origin, similar damping.
This should take down the ripple most of 40 dB. It
can work to set the filter higher, but the shifted poles
get closer to the switching frequency than I would
like to see.

That's were it becomes fun. With a few more
answers, I am inclined to simulate a controller
and idealization of your plant.

Following is source for an LTSPice simulation
(see http://www.linear.com/company/software.jsp )
with the 2 zeroes and 1 pole in H, and 1 pole
at 0) in G. This is not any kind of final design,
but it does demonstrate how easy it will be to
attain the performance so far mentioned. For
a real circuit, there may need to be a bit more
filtering to keep switching junk out of the first
near-differentiator (or it may be fine as is). It
will certainly work to use slower op-amps.

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TEXT -496 96 Left 0 !.step param GX 0 5 1
TEXT -496 128 Left 0 !.param LPFS=.1
========== end lcyank.asc ==============

The above simulation should be a convincing demonstration
that using the controller to get the PWM filtered output
response apparently desired by the OP is feasable and
unlikely to present serious problems. Obviously, gains
and maybe offsets will need adjustment once the VCVS
is replaced by the PWM IC. When current limiting is put
into place, some attention to limiting in the controller will
be in order. A sensitivity analysis for L and C variation
would be smart. It might be a good idea to make sure
no limit cycles are possible, using time domain simulation
and a range of step inputs.

 

[analog]

[For] academic purposes I am still curious about what other
approaches other than an equalizing network one might try to solve
the reactance problem? It seems to me that one approach might be
to try to sense the PWM output post-filter, and then compensate
for the peaking within the PWM amplifier control loop.

One can incorporate any number of LC output filter sections within
the feedback loop of an amplifier. Doing this requires sensing a
more or less orthogonal set of states for the output filter and
delivering them in a properly weighted measure of feedback and
feedforward terms to the error amplifier. Here is a link to my
illustrated explanation of this technique: (You may have to become
our newest group member to access this file ...it's free to join.)

http://groups.yahoo.com/group/LTspice/files/adventures with analog/class d audio/Leapfrog_Design.pdf

Do you have access to the binaries group? I could also post the PDF
there as well. In any case, here is the text sans illustrations:

The “Leapfrog” Method Of Switching
Amplifier Control Loop Design
[email protected] - 1996

The leapfrog design method extends active damping techniques
to incorporate an unlimited number of output filter sections
within a switching amplifier feedback loop. By working in
steps from the power switching stage outward, the process of
designing gain coefficients for each feedback filter component
is simplified to a first order problem. At each stage the
amplifier’s impedance characteristic leapfrogs between that
of current and voltage source (hence the name). The leapfrog
method breaks the design problem into manageable steps, and
turns what would otherwise be a practically intractable problem
with four, six or more independent variables, into a series of
straight­forward choices for each feedback coefficient.


Switching amplifiers are attractive for high power audio applications
because of their inherently low conduction/blocking losses. This
results from maintaining the output power devices in either a fully
saturated or cut-off state such that they never simultaneously support
large currents and voltages as is typical of standard linear audio
amplifiers. This switching characteristic can provide an important
efficiency advantage over standard linear amplifiers if the losses
from the switching transitions are also kept to a relatively low level.
Toward this end it is desirable to switch at as low of a frequency as
is compatible with closed-loop system bandwidth and output impedance
requirements (a switching amplifier is actually a high level digital
sampled data system with its ensuing Nyquist sampling effects which
limit maximum bandwidth to no more than one half the switching
frequency).

Another significant complication often arises because of the need
to strictly limit the level of switching ripple components on the
amplifier’s output without restricting the amplifiers ability to
deliver rail-to-rail audio signals at 20 kHz. This requires the use
of an output recovery filter with multiple L/C sections and with pole
locations just above the audio pass band. To optimize closed-loop
system bandwidth and output impedance necessitates that the feedback
system be able to track and compensate the rapid phase shift stemming
from the output filter’s high Q poles and zeros, the location of
which will vary dynamically due to current and temperature dependent
shifting of the component values. Note that, in high efficiency power
applications, dissipative elements may not be readily used in the
recovery filter to control L/C resonances.

This has not been an easy problem to solve using traditional tech-
niques. Standard compensation methods with op­amps, resistors and
capacitors fail because it is not possible to match and track the
frequency characteristics of the high Q L/C filter sections.
Typically, the amplifier’s feedback loop will include none or only
the first of the output filter sections within its control loop.
This approach degrades the accuracy of the amplified audio signal.

In some prior switching amplifiers, the control loop has been
designed using active damping techniques to track filter component
shifts, manage output filter Q and extend bandwidth. With this
method, a sensed signal directly proportional to output filter
capacitor current is an integral part of the feedback loop. This
ensures direct, accurate tracking and control of output filter
resonances, and allows maximum loop gain-bandwidth in the face of a
single L/C filter section.

The leapfrog design method described below extends the active damping
technique to incorporate an unlimited number of output filter
sections within the feedback loop, and describes how to choose the
gain coefficients for each feedback filter component by working in
steps from the power switching stage outward. As the gain coefficient
for each component is chosen, and that component is incorporated
within the amplifier’s black box boundary, the impedance characteristic
the amplifier presents at its output changes to a current source if the
component is an inductor or to a voltage source if the incorporated
component is a capacitor. As each component is swallowed up, the
overall closed loop bandwidth must be reduced by a small factor (about
1.5 or so). Thus, the amplifier’s output characteristic leapfrogs
between that of a current and voltage source (hence the name). This
simplifies the design process of each succeeding gain coefficient to a
first order problem. The leapfrog method breaks the design problem
into manageable steps, and turns what would otherwise be a practically
intractable problem with four, six or more independent variables, into
a series of straight­forward choices for each feedback coefficient.

The figure below will be used to illustrate the leapfrog design process
for a four-element ladder filter network. Working from the power
switch to the output (left to right), the voltage command to the power
stage/modulator is the sum of the positive feedback signal of the
voltage appearing on the output side of L1 and the negative feedback
signal of the inductor current. Note that the modulator and totem
pole output stage is approximated as a voltage controlled voltage
source with delay due to sampled data nature of the pulse width
modulation process. The unity gain positive feedback term of the load
side voltage from the inductor serves to keep the voltage across the
inductor (and hence its current) constant in the face of load side
voltage perturbations. The negative feedback signal of inductor
current roles off with a single pole due to the rising impedance of
inductor L1. Gain K1 is set so that loop gain falls to zero somewhat
before half the switching frequency (where the switching delay adds 180
degrees phase shift). As the inductor is merged into the black box of
the amplifier on the left hand side, the resulting equivalent voltage
controlled current source is shown below feeding the next filter
element C2.

Next, capacitor C2 is incorporated into the equivalent circuit in
exactly a dual nature. Looking at the following figure, the unity
gain positive feedback term of load side current out of the capacitor
functions to null net current through the capacitor in spite of sudden
changes in load current, minimizing the resulting voltage fluctuations.
The negative feed­back term of capacitor voltage roles off with a
single pole due to the falling impedance that capacitor C2 presents to
the controlled current source. Gain K2 for this feedback path is set
so that loop gain falls to zero at about two thirds of the current
source’s bandwidth. The resulting equivalent voltage controlled
voltage source is shown below feeding the next filter element L3.

Now the leapfrog method has come full circle to the starting conditions
of a controlled voltage source feeding an inductor element in an LC
filter ladder. Just as before, this element is incorporated into the
system by applying the appropriate amounts of positive and negative
feedback. Gain K3 for this feedback path is set so that closed loop
gain is about two thirds of what it was before. The resulting
equivalent voltage controlled current source is shown below feeding
the next filter element C4.

The process continues until all the filter elements are incorporated
into the amplifier, yielding a well controlled, component insensitive,
switching amplifier with the maximum possible bandwidth. These
advantages come at a cost of an extensive feedback network distributed
throughout the switching amplifier’s recovery filter ladder.

In practice, both the sensing and feedback amplifier circuitry can be
greatly simplified by combining adjacent signal paths. In particular,
combining stages removes the need to reproduce dc signals in the
sensing circuitry. Recognizing that the difference of inductor
currents must flow through the capacitor on the common node between
adjacent stages justifies using a simple current transformer to sense
this difference current. Likewise, recognizing that the difference
of capacitor voltages must appear across the interposing inductor
justifies using a simple floating winding to sense the difference
voltage.

All of the distributed gain terms are easily consolidated into a
single summing amplifier by simply accounting for the cumulative gain
terms in the path for each signal as shown above.

Following these constructs results in a switching amplifier system that
is both practical and simple, yet easily accommodates a recovery ladder
filter network of any length within its feedback path.

The following schematics were simulated in LTspice in order to
demonstrate and confirm the principles of the leapfrog method of
switching amplifier design. As expected, the simulation output from
the three variations was absolutely identical, verifying the validity
of the topological manipulations.

Typical output from ac frequency response and 10kHz square wave
transient response is presented below, with each showing the effect of
stepping the load resistor from 1 to 8 ohms. Note that fs represents
the effective sampling frequency which may be quite different from the
nominal switching frequency. For example, in a free-running, self-
oscillating design, the effective sampling frequency would be very
close to the lowest switching frequency during dynamic excursions and
not the typically 3-to-4-times higher quiescent operating frequency.
Likewise td represents the effective worst-case delay rather than the
typical delay. Thus, the rather high fs and low td of the simulation
would be difficult to achieve in practice unless the design employed
multiple, parallel, staggered phase output stages feeding the recovery
filter. (This technique multiplies the sampling frequency by the
number of staggered phase output stages.)

 

[analog]

[For] academic purposes I am still curious about what other
approaches other than an equalizing network one might try to solve
the reactance problem? It seems to me that one approach might be
to try to sense the PWM output post-filter, and then compensate
for the peaking within the PWM amplifier control loop.

At the end of this post is an LTspice schematic files that is an
example of a large signal frequency response analysis of a class d
amplifier.

This simulation uses the recently derived* mathematically correct
swept sine time domain source in conjunction with a very fast
running LTspice A-device to analyze the large signal behavior of a
self oscillating class d amplifier under a variety of dc bias levels
(approximates high frequencies riding on a large bass signal). The
sine source is swept logarithmically from 2.5kHz to 250kHz (25kHz is
center screen).

Many weird large signal effects (such as frequency shift, aliasing,
pulling and lock) are clearly visible. Note that none of these
would be evident in a small signal ac analysis.

When properly set up, the A-device simulates a realistic delay while
efficiently allowing maximum step size between switching edges and
simultaneously capturing edge timing with great fidelity. This makes
successive design iterations possible with almost no waiting.

Regards -- analog

*Earlier (in the LTspice Yahoo Group) I was trying to generate a
logarithmically swept sine source that would produce the equivalent
of a small signal linearized frequency-based ac analysis in a time
domain-based transient analysis. My intuition had led me to expect
that given a slow enough sweep, the "doppler effect" on the swept
sine wave should have been small enough to ignore.

The sort of .tran swept sine source I was seeking would allow direct
frequency response analysis of such non linear circuits as switching
power supplies or class D amplifiers without having to replace them
with "equivalent" linear models.

I am fortunate enough to have a good personal friend (known as "The
Phantom" on sci.electronics.design, etc.) who is both an excellent
analog engineer and a wizard with Mathmatica. With his assistance
I now have an exact expression for a logarithmically swept sine wave
source in the time domain. This technique makes a *very* nice
addition to LTspice's burgeoning tool set.

Here are the basic equations:

The sine wave: V(t) = Vp*sin(2*pi*f*t); f normally constant

The sweep function: f(t) = f1*(f2/f1)**(t/dt); where
f1 is the start frequency
f2 is the stop frequency
dt is the sweep duration

As noted, simply combining the two equations squeezes the
resulting sine wave, leading to frequency "compression".

V(t) = Vp*sin(2*pi*f1*(f2/f1)**(t/dt)*t); WRONG!!

Here is the correct form:

V(t) = Vp*sin(2*pi*f1*(f2/f1)**(t/dt)*dt/ln(f2/f1)); mmm..good

~~~~ UcD_swept_sine_test.asc (cut&paste & mind the word wrap) ~~~~
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TEXT 248 320 Left 0 !.param Vdc=0 Vp=1 f1=2k5 f2=250k Td=4m
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TEXT 704 -32 Center 0 ;35kHz
TEXT 480 -32 Center 0 ;400kHz
TEXT 64 -336 Left 0 ;This circuit demonstrates the use of a swept sine source to test \nthe large signal frequency response of an idealized UcD180 style \nself oscillatiing class D amplifier, as a function of input amplitude,\ninput offset, and output load.
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TEXT 408 -392 Center 0 ;Swept Sine Analysis - analogspiceman 2005
TEXT 248 352 Left 0 !.step param Vdc list 0 -4 -8
RECTANGLE Normal 672 -368 144 -416 1

 

[analog]

[For] academic purposes I am still curious about what other
approaches other than an equalizing network one might try to solve
the reactance problem? It seems to me that one approach might be
to try to sense the PWM output post-filter, and then compensate
for the peaking within the PWM amplifier control loop.

At the end of this post is an LTspice schematic file that is an
example of a large signal frequency response analysis of a class d
amplifier.

Whoops! Can't see the forest for the trees... I forgot to mention
that the main point of the above is that it shows a design approach
that incorporates the LC output filter within the feedback loop as
an integral part of its self oscillating mechanism (note that this
method is problematic if fixed frequency operation is required whereas
the leapfrog method mentioned in an earlier post is perfectly general
in this regard). -- analog

 

[analog]

[For] academic purposes I am still curious about what other
approaches other than an equalizing network one might try to solve
the reactance problem? It seems to me that one approach might be
to try to sense the PWM output post-filter, and then compensate
for the peaking within the PWM amplifier control loop.

Here's an example of a self oscillating class d amplifier 'a la the
leapfrog method that both contains the output filter within its
feedback loop and provides integral output current limiting:

http://groups.yahoo.com/group/LTspi... analog/class d audio/ClassD_LeapFrog_UcD.asc

~~~~ ClassD_LeapFrog_UcD.asc (cut&paste & mind the word wrap) ~~~~
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SYMATTR Value 2N4401
SYMBOL nmos 384 -144 R0
WINDOW 3 56 32 Left 0
WINDOW 0 57 64 Left 0
SYMATTR Value STP14NF12
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SYMBOL pnp 272 80 M180
WINDOW 0 51 64 Left 0
WINDOW 3 51 32 Left 0
SYMATTR InstName Q8
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SYMBOL diode 256 -48 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D6
SYMATTR Value 1N914
SYMBOL pnp 64 -96 M180
WINDOW 0 51 64 Left 0
WINDOW 3 51 32 Left 0
SYMATTR InstName Q7
SYMATTR Value 2N4403
SYMBOL res 256 144 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
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SYMBOL cap 96 160 R270
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WINDOW 123 32 0 VLeft 0
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SYMBOL diode -80 224 M180
WINDOW 0 48 48 Left 0
WINDOW 3 48 24 Left 0
SYMATTR InstName D4
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WINDOW 3 32 56 VTop 0
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WINDOW 3 -32 56 VBottom 0
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SYMBOL ind2 464 208 R270
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SYMATTR SpiceLine Rser=10m Rpar=10k
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WINDOW 0 -32 32 Right 0
WINDOW 3 -32 64 Right 0
SYMATTR InstName Q4
SYMATTR Value 2N5550
SYMBOL npn -480 352 R0
WINDOW 0 -32 32 Right 0
WINDOW 3 -32 64 Right 0
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SYMATTR Value 2N5550
SYMBOL res -400 528 R0
SYMATTR InstName R9
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SYMBOL res 240 -80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R12
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SYMBOL res 48 -144 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
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WINDOW 3 -3 32 VBottom 0
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SYMATTR Type diode
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SYMBOL pnp 272 576 M180
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WINDOW 3 51 32 Left 0
SYMATTR InstName Q10
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SYMBOL diode 256 448 R270
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WINDOW 3 0 32 VBottom 0
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SYMATTR Value 1N914
SYMBOL pnp 64 400 M180
WINDOW 0 51 64 Left 0
WINDOW 3 51 32 Left 0
SYMATTR InstName Q9
SYMATTR Value 2N4403
SYMBOL res 256 640 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
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SYMATTR Value 220
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WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
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SYMBOL res 48 352 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
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SYMATTR Value 150
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WINDOW 0 51 64 Left 0
WINDOW 3 51 32 Left 0
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SYMATTR Value 2N5401
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SYMATTR Value 2N5401
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WINDOW 3 0 32 VBottom 0
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WINDOW 3 0 32 VBottom 0
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SYMATTR Value 3m
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WINDOW 3 -3 32 VBottom 0
SYMATTR InstName D7
SYMATTR Value BAT54
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SYMATTR Type diode
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SYMATTR Value PULSE({-a} {a} 0 1u 1u 49u 100u)
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SYMATTR Value 2N5401
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WINDOW 3 51 64 Left 0
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SYMATTR Value 2N5550
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WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
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SYMATTR Value 100
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WINDOW 3 36 40 Left 0
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SYMATTR Value 100
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WINDOW 3 51 32 Left 0
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SYMATTR Value 2N5401
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WINDOW 3 51 64 Left 0
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SYMATTR Value 2N5550
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SYMATTR InstName R22
SYMATTR Value 100
SYMBOL res 752 528 R0
SYMATTR InstName R25
SYMATTR Value 100
SYMBOL res 752 -272 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R21
SYMATTR Value 50m
SYMBOL res 752 624 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R24
SYMATTR Value 50m
SYMBOL res 624 352 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R19
SYMATTR Value 10k
SYMBOL cap 672 112 M180
WINDOW 0 24 64 Left 0
WINDOW 3 24 8 Left 0
SYMATTR InstName C7
SYMATTR Value 150p
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WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R14
SYMATTR Value 10
SYMBOL cap 368 -240 M0
WINDOW 0 32 16 Left 0
WINDOW 3 32 48 Left 0
SYMATTR InstName C5
SYMATTR Value 22p
SYMBOL res 368 416 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R18
SYMATTR Value 10
SYMBOL cap 368 256 M0
WINDOW 0 32 16 Left 0
WINDOW 3 32 48 Left 0
SYMATTR InstName C6
SYMATTR Value 22p
SYMBOL res 64 16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R10
SYMATTR Value 3k3
SYMBOL res -592 16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R8
SYMATTR Value 3k3
SYMBOL res -1024 -224 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL Misc\\xvaristor -848 112 M90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName D1
SYMATTR Value limit
SYMATTR Prefix D
SYMBOL res -736 16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R7
SYMATTR Value 3k3
SYMBOL cap -848 -144 M0
WINDOW 3 32 48 Left 0
WINDOW 0 32 16 Left 0
SYMATTR Value 100p
SYMATTR InstName C1
SYMBOL res -880 64 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 4k3
SYMBOL res -848 -144 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R5
SYMATTR Value 1k5
SYMBOL res -736 -80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R6
SYMATTR Value 28k7
SYMBOL res -1024 -128 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res -880 -32 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value 3k3
SYMBOL cap -208 64 R0
SYMATTR InstName C3
SYMATTR Value 47p
SYMBOL cap -560 64 M0
SYMATTR InstName C2
SYMATTR Value 47p
SYMBOL Opamps\\opamp -1088 -80 R0
WINDOW 3 0 96 Left 0
SYMATTR InstName U1
SYMATTR SpiceLine ""
SYMATTR SpiceLine2 ""
SYMBOL Opamps\\opamp -800 160 R0
WINDOW 3 0 96 Left 0
SYMATTR InstName U2
SYMATTR SpiceLine ""
SYMATTR SpiceLine2 ""
SYMBOL res 864 192 R0
SYMATTR InstName Ro
SYMATTR Value {Ro}
TEXT -1168 688 Left 0 !.tran 0 225u 25u uic
TEXT -120 672 Left 0 !.model STP14NF12 vdmos (Rg=5 Rd=90m Rs=70m Vto=3.5 Kp=3\n+ Cgdmax=200p Cgdmin=20p Cgs=420p Cjo=60p Is=10p Rb=140m)
TEXT -1168 312 Left 0 !.model limit d(Ron=1u Vfwd=5 Vrev=5)
TEXT -1168 352 Left 0 !.subckt opamp 1 2 3\nG1 0 3 2 1 10k\nC1 3 0 160µ Rpar=100\nD1 3 0 lim\n.model lim d(Ron=1u Vfwd=12 Vrev=12)\n.ends opamp
TEXT -1168 648 Left 0 !.step param Ro list 1G 6 1u
TEXT -1168 624 Left 0 !.param a=5 Ro=6
TEXT -384 -312 Center 0 ;UcD180 Class D Amplifier Power Stage \ndriven by LeapFrog control\nby analogspiceman, March, 2005
TEXT -1168 528 Left 0 ;10kHz square wave response into\nopen, nominal, and short circuits.\nPlot V(o) and I(L1)

 

[analog]

[For] academic purposes I am still curious about what other
approaches other than an equalizing network one might try to solve
the reactance problem? It seems to me that one approach might be
to try to sense the PWM output post-filter, and then compensate
for the peaking within the PWM amplifier control loop.

Here's an example of a self oscillating class d amplifier 'a la
the leapfrog method that both contains the output filter within
its feedback loop and provides integral output current limiting:

[cut first example]

Here's an example of a self oscillating class d amplifier based
on the UcD180 design that contains the output filter within its
feedback loop (provides no inherent output current limiting):

This and the previously posted schematic are detailed simulation
files for full bandwidth 180W class-d amplifiers. The UcD is
available for do-it-yourselfers at low cost from http://www.hypex.nl
and seems to be a fine product.

For more information see their web site or read about it and
other home brew projects on the do-it-yourselfer's audio forum at
http://www.diyaudio.com under the Class D section. (Note: I have no
commercial affiliation with either of these two entities - I just
am fascinated with class-d amplifier design.)

The two simulation files look at amplifier response into a 10kHz
square wave at open, nominal and short circuits. Both amplifiers
perform similarly at full load, but at open and short circuits...

Well, I'll leave it for you to be the judge.

Regards -- analog(spiceman)

http://groups.yahoo.com/group/LTspice/files/adventures with analog/class d audio/ClassD_UcD180.asc

~~~~ ClassD_UcD180.asc (cut&paste & mind the word wrap) ~~~~
Version 4
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SYMATTR Value {Ro}
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WINDOW 3 32 56 VTop 0
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TEXT -1056 616 Left 0 !.tran 0 275u 75u uic
TEXT -256 688 Left 0 !.model STP14NF12 vdmos (Rg=5 Rd=90m Rs=70m Vto=3.5 Kp=3\n+ Cgdmax=200p Cgdmin=20p Cgs=420p Cjo=60p Is=10p Rb=140m)
TEXT -304 584 Left 0 ;Io 7Arms 10Ap
TEXT -304 520 Left 0 ;65dB PSRR
TEXT -304 552 Left 0 ;93 % efficiency
TEXT -392 -256 Center 0 ;UcD180 Class D Amplifier Schematic \nmy guesstimate by analogspiceman\nMarch, 2005
TEXT -304 488 Left 0 ;Fosc 415kHz
TEXT -1056 584 Left 0 !.step param Ro list 1G 6 1u
TEXT -1056 480 Left 0 ;10kHz square wave response into\nopen, nominal, and short circuits.\nPlot V(o) and I(L1)

 

[Genome]

[Garbage Spice Simulation Snipped]

The above simulation should be a convincing demonstration
that using the controller to get the PWM filtered output
response apparently desired by the OP is feasable and
unlikely to present serious problems. Obviously, gains
and maybe offsets will need adjustment once the VCVS
is replaced by the PWM IC. When current limiting is put
into place, some attention to limiting in the controller will
be in order. A sensitivity analysis for L and C variation
would be smart. It might be a good idea to make sure
no limit cycles are possible, using time domain simulation
and a range of step inputs.

SNORT!!!!

I don't know which three legged horse you rode in on but perhaps you should
mount up and ride back out again......

Let's just see the error report for your circuit,


Questionable use of curly braces in "c1 vx 0 {7.2?/lpfs}"
error: Error: unknown token in: "7.2[?]/lpfs"
Questionable use of curly braces in "l2 va vx {22.5?/lpfs}"
error: Error: unknown token in: "22.5[?]/lpfs"
Questionable use of curly braces in "b1 va 0 v={{gx}*v(vc)}"
error: Error: undefined symbol in: "(gx)*[v](vc)"
Circuit: * C:\news\carlen\larry.asc

Error on line 4 : c1 vx 0 (7.2?/lpfs)
Unknown parameter "/lpfs"
Error on line 5 : l2 va vx (22.5?/lpfs)
Unknown parameter "/lpfs"

Spice doesn't generate these sort of reports for general entertainment. It
gives you indications about ERRORS in your circuit. The analysis might run
but there is the old adage about 'garbage in, garbage out'.

Shall we try again?

Instead of 7.2?/LPFS try 7u2/LPFS
Instead of 22.5?/LPFS try 22u5/LPFS
Instead of .param LPFS=.1 try .param LPFS=1
Instead of V={GX*V(VC)} try V=GX*V(VC)
L1, that 250? inductor will be interpreted as a 250H inductor. Try the
proper value of 250u.

You could write V=80*V(VC) for B1 and include a note to the effect that you
are assuming that the peak to peak amplitude of the modulator triangle wave
is 2V and you are assuming a bridge supply of 80V. Then you might as well
just use the proper values for the components.

Why you are including all this knob end when it's not really necessary is a
mystery known only to yourself. Are you pretending to be clever or are you
being deliberately stupid so that someone will talk to you?

Oh, R2 serves no visible purpose.

So...... Let's just fix and tidy up your circuit.

Version 4
SHEET 1 880 880
WIRE -640 112 -672 112
WIRE -640 192 -640 112
WIRE -640 288 -640 272
WIRE -544 592 -544 560
WIRE -544 704 -544 672
WIRE -544 736 -544 704
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Much prettier.

You're doing it again, I've told you about this before. You are plotting the
closed loop response rather than measuring the loop response. See how I've
inserted an AC source, VAC, in the loop.

Do an AC analysis, the circuit as given is set up to do that, and plot
V(VERR)/V(VC). Notice how it crosses over at 400KHz with little to no phase
margin.

Let's just ignore the fact that this is supposedly a model of a PWM
amplifier operating at 125KHz.

Don't believe it?

Right Click on .ac dec 20 1 500K and turn it from a Spice Directive to a
Comment. Right Click on .tran 0 100u 0 and turn it from a Comment to a Spice
Directive.

Run the transient analysis and plot V(VERR). You will notice that it's
ringing a bit. Do an FFT on it...... That's right it's ringing at 400KHz,
the loop crossover frequency.

You've, sort of, got a bit of it right. But, seriously, your bunch has no
bananas. Before you rush off and intersperse my wonderful critique of your
mess with 800 lines of blibble.... try to shut up.

DNA

 

[Larry Brasfield]

[Garbage Spice Simulation Snipped]

The above simulation should be a convincing demonstration
that using the controller to get the PWM filtered output
response apparently desired by the OP is feasable and
unlikely to present serious problems. Obviously, gains
and maybe offsets will need adjustment once the VCVS
is replaced by the PWM IC. When current limiting is put
into place, some attention to limiting in the controller will
be in order. A sensitivity analysis for L and C variation
would be smart. It might be a good idea to make sure
no limit cycles are possible, using time domain simulation
and a range of step inputs.

....
Let's just see the error report for your circuit,

Questionable use of curly braces in "c1 vx 0 {7.2?/lpfs}"
error: Error: unknown token in: "7.2[?]/lpfs"
Questionable use of curly braces in "l2 va vx {22.5?/lpfs}"
error: Error: unknown token in: "22.5[?]/lpfs"
Questionable use of curly braces in "b1 va 0 v={{gx}*v(vc)}"
error: Error: undefined symbol in: "(gx)*[v](vc)"
Circuit: * C:\news\carlen\larry.asc

Error on line 4 : c1 vx 0 (7.2?/lpfs)
Unknown parameter "/lpfs"
Error on line 5 : l2 va vx (22.5?/lpfs)
Unknown parameter "/lpfs"

Spice doesn't generate these sort of reports for general entertainment. It
gives you indications about ERRORS in your circuit.

My simulation ran without diagnostics. There were
no '?' characters in the file I pasted into my post.
After filtering your post for useful content, I can
see that some process between my clipboard and
the post retrieved into my newsreader has replaced
certain ASCII characters with '?'. That is something
worth knowing, so, despite your caterwauling post,
I thank you for the tip.

The analysis might run
but there is the old adage about 'garbage in, garbage out'.

Such wisdom. Another gem.

Shall we try again?

Instead of 7.2?/LPFS try 7u2/LPFS
Instead of 22.5?/LPFS try 22u5/LPFS
Instead of .param LPFS=.1 try .param LPFS=1
Instead of V={GX*V(VC)} try V=GX*V(VC)
L1, that 250? inductor will be interpreted as a 250H inductor. Try the
proper value of 250u.

You could write V=80*V(VC) for B1 and include a note to the effect that you
are assuming that the peak to peak amplitude of the modulator triangle wave
is 2V and you are assuming a bridge supply of 80V. Then you might as well
just use the proper values for the components.

I could, but that goes beyond the stated purpose
of my post. I could design the whole circuit, but
there would be no purpose to it beyond a silly
attempt to impress you and your ilk.

["... stupid ..." questions cut.]

Oh, R2 serves no visible purpose.

It does if a behavioral voltage source is the only
consumer of what drove R2.

So...... Let's just fix and tidy up your circuit.

[Cut circuit which also suffered from posting path
issues, but does simulate with group delay performance
way outside of anything the OP stated or implied.]

Much prettier.

So you say. To simulate the PWM, I would revert
the VCVS back to a behavioral source so that the
PWM delay characteristic could be added.

You're doing it again, I've told you about this before. You are plotting the
closed loop response rather than measuring the loop response. See how I've
inserted an AC source, VAC, in the loop.

The loop gain is not especially interesting, being readily
determined by inspection. I made no effort to plot it.

Do an AC analysis, the circuit as given is set up to do that, and plot
V(VERR)/V(VC). Notice how it crosses over at 400KHz with little to no phase
margin.

What you call VERR is not what is commonly called the
error. As for doing AC analysis, I don't know quite what
you simulated, but my controller, with loop gain set to bring
the complex poles well into the LHP, has plenty of phase
margin and a well behaved step response.

[More of same cut.]
[More folderol cut.]

 

[Chris Carlen]

[...] It seems to me that one approach might be to try to sense the
PWM output post-filter, and then compensate for the peaking within
the PWM amplifier control loop.

Do you have access to the binaries group? I could also post the PDF
there as well. In any case, here is the text sans illustrations:

The “Leapfrog” Method Of Switching
Amplifier Control Loop Design
[email protected] - 1996

The leapfrog design method extends active damping techniques
to incorporate an unlimited number of output filter sections
within a switching amplifier feedback loop. By working in
steps from the power switching stage outward, the process of
designing gain coefficients for each feedback filter component
is simplified to a first order problem. At each stage the
amplifier’s impedance characteristic leapfrogs between that
of current and voltage source (hence the name). The leapfrog
method breaks the design problem into manageable steps, and
turns what would otherwise be a practically intractable problem
with four, six or more independent variables, into a series of
straight­forward choices for each feedback coefficient.

Okay, Chris, I have attached the PDF (you may have to go over to
alt.binaries.schematics.electronic to get it).

Thanks, analog.

I will have to process all this in time.


Good day!



--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

 

[Larry Brasfield]

I need to spend some more time with pencil and paper to understand
how the controller can "move the poles" of the filter.

The LTSpice simulation I posted Sunday, with suitable
corrections for some posting anomalies, can be used
to show how the poles move versus loop gain and see
the range of loop responses available.

Below, (after posting, I hope), is a revised form of the
same controller with a pair of solutions selected by NS.
(Loop gain GX, LPF scaling LPFS, and scaling of the
zero pair and realization pole, ZW, are all set by NS.)
I've set it up so that the controller response can also be
scaled (approximately, ignoring op-amp poles), not just
the LC LPF. This makes it more convenient to simulate
for the output filter you may want to actually build. As
you can see, it is quite possible to move the LPF poles
closer to the origin as I have suggested.

The group delay is (about) either 33uS or 50uS and
flat within a few hundred nS out to 400 Hz. You might
note that, after shifting by the controller, the response is
close to what your bare LC LPF was doing.

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========== end lcyanka.asc =============

There are a number of steps remaining between the above
and a real circuit. The scaling between the controller and
the PWM does not reflect your 80V output range. There
should be some careful attention given to limiting behavior
because the loop is not stable for a range of lower loop
gain values. (The LC poles move into the RHP and back
into the LHP as loop gain is increased from 0.) This means
that limiting in an unfortunate location could serve to reduce
the loop gain and permit what is known as a limit cycle
oscillation. It may also be necessary to introduce some
additional low pass filtering to keep the chop frequency
from appearing too much at the output of the controller.

 

[Chris Carlen]

Yes, tight DC performance is needed. Gain can vary a few % but offset not.

There are also nonlinearities in the transfer of the SA60 that should be
servoed out. Thus, an integrator is desired.

Upon further reflection, an integrator in the forward
path to get precise gain and offset is no big deal.
With a little tweaking to get the 3 poles properly
related to each other, the group delay easily falls
within a couple uS band out to 400 Hz. With even
more effort, (ajusting the zero positions and care
in setting loop gain), the 3 poles could be made to
conform to a cookbook equiripple group delay LPF.
From the initial results of simulation, I see no need
to bother with that mathematical exercise.

...

I don't want to use a gapped core since they don't work well with the
physical constraints. I want a low profile off the PCB. I am choosing
to use a Magnetics Inc. Kool-mu toroid core. I originally calculated
for 100kHz switching freq., 10kHz LPF cutoff, so 27uH. Bumping the
inductance down a little bit should make the same cores actually hold
better than the original 75% of inductance at 10A. Haven't done the
math again yet, but hopefully about 80%.

For the simulation included below, I set the LC poles
about 10 times closer to the origin, similar damping.
This should take down the ripple most of 40 dB. It
can work to set the filter higher, but the shifted poles
get closer to the switching frequency than I would
like to see.

But that doesn't help much. A pair of 225uH inductors + 2x72uF of caps
that can handle 10A is likely to be larger than my equalizer and may
very well dissipate a lot of power anyway. Maybe the equalizer isn't so
bad. Remember, for the real application, there really will be almost no
frequency content above 150Hz. The extended bandwidth is just for phase
flatness at the low end.

That's were it becomes fun. With a few more
answers, I am inclined to simulate a controller
and idealization of your plant.

Following is source for an LTSPice simulation
(see http://www.linear.com/company/software.jsp )
with the 2 zeroes and 1 pole in H, and 1 pole
at 0) in G. This is not any kind of final design,
but it does demonstrate how easy it will be to
attain the performance so far mentioned. For
a real circuit, there may need to be a bit more
filtering to keep switching junk out of the first
near-differentiator (or it may be fine as is). It
will certainly work to use slower op-amps. [edit]
The above simulation should be a convincing demonstration
that using the controller to get the PWM filtered output
response apparently desired by the OP is feasable and
unlikely to present serious problems. Obviously, gains
and maybe offsets will need adjustment once the VCVS
is replaced by the PWM IC. When current limiting is put
into place, some attention to limiting in the controller will
be in order. A sensitivity analysis for L and C variation
would be smart. It might be a good idea to make sure
no limit cycles are possible, using time domain simulation
and a range of step inputs.

Ok, other than the question marks to which Genome unsurprisingly
overreacted, I can use the simulation.

Thanks for the demo. I think I can learn to compensate in this manner.
For now, it seems to my advantage to procede with the simple but
functional circuit that I'm using. But your input has provided material
for further investigation.

The smart thing to do would be to make the PCB design flexible enough to
implement several compensation approaches. I'm already planning to make
it switchable to become a current source. That would ultimately make
more sense for a position servo. But for now I'm in voltage drive due
to legacy issues.


Thanks for the input.


Good day!





--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

 

[Nico Coesel]

Yes, tight DC performance is needed. Gain can vary a few % but offset not.

Then you should use the smallest possible inductors because of the DC
resistance.

But that doesn't help much. A pair of 225uH inductors + 2x72uF of caps
that can handle 10A is likely to be larger than my equalizer and may
very well dissipate a lot of power anyway. Maybe the equalizer isn't so
bad. Remember, for the real application, there really will be almost no
frequency content above 150Hz. The extended bandwidth is just for phase
flatness at the low end.

Then why bother with the filter so much? Any filter will suffer from
non-linearities in the filter components and the load (especially the
filter components you describe) at these power levels. Also, I suspect
the load will not be a constant inductor which adds extra
non-linearities as well which in turn will affect the filter.

Besides, 225uH inductors and 72uF capacitors sound way too large to
me. I expect the inductors 10uH to 47uH and the capacitors from 1uF to
10uF.

I think it's better to size the inductors and capacitors according to
the amount of energy they should store and the amount of ripple you
tolerate like in a switching power supply.
Did you already read my answer to John Woodgate?

"In other words, butterworth, bessel and zobel look nice in theory,
but their practical use is very limited when it comes to class D
amplifiers.

I found out that using some inductors and capacitors to smear the
pulses into something that looks like a signal and using a common mode
filter as a final stage to get rid of the HF components works much
better."

 

[Chris Carlen]

Then you should use the smallest possible inductors because of the DC
resistance.


Then why bother with the filter so much? Any filter will suffer from
non-linearities in the filter components and the load (especially the
filter components you describe) at these power levels. Also, I suspect
the load will not be a constant inductor which adds extra
non-linearities as well which in turn will affect the filter.

Besides, 225uH inductors and 72uF capacitors sound way too large to
me. I expect the inductors 10uH to 47uH and the capacitors from 1uF to
10uF.

I'm not bothering with the filter at all. My filter is reasonable, at
22.5uH and 7.2uH. Larry proposed making the values 10x larger in order
to demonstrate his post-filter compensation idea.

But that doesn't seem attractive to me since the gain of eliminating the
equalizer (just to be clear, the "equalizer" is the series RC across the
load RL to cancel out most of the reactance of the L) is offset by
unrealistic LC filter values.

It is also true that the load inductance is likely to be non-linear due
to the fact that it is a PM linear motor. I don't expect perfect
performance from the filter. Nor should it be a problem because any of
the wigglies in the overall response are at much higher frequencies than
the application involves. The only time they will become relevant is in
other potential applications where the bandwidth approaches the limits
of the amp.

I think it's better to size the inductors and capacitors according to
the amount of energy they should store and the amount of ripple you
tolerate like in a switching power supply.
Did you already read my answer to John Woodgate?
Yes.

"In other words, butterworth, bessel and zobel look nice in theory,
but their practical use is very limited when it comes to class D
amplifiers.

I found out that using some inductors and capacitors to smear the
pulses into something that looks like a signal and using a common mode
filter as a final stage to get rid of the HF components works much
better."

Are you saying that you would incline toward overdamping the output
filter so that it's response is not so sensitive to load reactance, and
just accepting the increased ripple that would result?

Or perhaps rather, putting the output filter cutoff at a much higher
frequency than the amp's bandwidth so that any peaking or drooping
caused by load reactance is out of band anyway?



Good day!



--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.