PSpice: Simulation of differential ECL gates

[[email protected]]

Hi.

I currently simulate digital ECL circuits using ideal parts from
"dig_prim.olb". I put a DELAY on each gate's output to simulate the
propagation delay. This is important because the propagation delays
are in the dimension of a clock cycle.

Is anyone out there who also uses PSpice to simulate ECL circuits?
Does anyone know a more appropriate way therefor? Fore example the
availability of true ECL models?


Regards,
Norbert

 

[Charlie E.]

Hi.

I currently simulate digital ECL circuits using ideal parts from
"dig_prim.olb". I put a DELAY on each gate's output to simulate the
propagation delay. This is important because the propagation delays
are in the dimension of a clock cycle.

Is anyone out there who also uses PSpice to simulate ECL circuits?
Does anyone know a more appropriate way therefor? Fore example the
availability of true ECL models?


Regards,
Norbert

Last time I looked there was an ECL library, so, yes, there are true
ECL libraries available. I never did that much simulation with them
though, although they are included in the digio.lib, and they took
great pains (and it was painful!) to make the levels come out right.

Charlie
Edmondson Engineering Inc.

 

[[email protected]]

Thanks for your response, Charlie.

It looks like the library is actually named "dig_io.lib" in OrCAD 16.

 

[[email protected]]

The library seems to be "dig_ecl.lib", not "dig_io.lib".

 

[[email protected]]

Some of us have our own personalized 10K, 100K plus ECLIPS ;-)

Do you mean ECLinPS? I cannot find (P)Spice models for ECLinPS.

 

[[email protected]]

I rolled my own, but I'm in the chip design business ;-)

How complete is your "own" ECLinPS library?

Could you send me a copy of it?

 

[[email protected]]

There are IBIS models available from OnSemi:
http://www.onsemi.com/pub_link/Collateral/MC100EP05D_33.IBS

But as far as I know this format is not supported by PSpice.

 

[Charlie E.]

PSpice does not support IBIS models.

...Jim Thompson

Also, remember, IBIS is purely an I/O model, not any type of form or
functionaliity, including internal delays and timing. they are
designed for signal integrity purposes, only.

Charlie

 

[krw]

Yep. In other words, totally useless for anything other than PCB
track analysis.

They're useful in designing the opposite end, as well. IOW,
"purely I/O models". ;-)