programmable current limit for push pull output stage

[yw]

Hello experts,

I am working on a circuit that will amplify pulse signals to +/-45V
range to drive a capacitive load. The load is of a range that is less
than 5uF. The output buffer stage is BJT push pull pair class A. I am
having trouble to design a circuit that can limit the output current
within a range of 0-2A with 100mA step. Obviously the output current
limit should be controlable by a controlled voltage or current source,
but not hard coded by sensing resistor that control the Vbe of the
current limit BJT.

What I am doing right now is using a high CM input instrument amplifier
to isolate the voltage drop on the current limiting sensing resistor.
The REF input of the INA is connected with a controlled voltage source.
The output of the INA is then connected with the Gate of a MOSFET. The
MOSFET's D is connected to the base of BJT at the push pull out put
stage and the MOSFT's S is connected with the GND. By control the
voltage that is input into REF pin I can shift the INA's output, hence
to control the Vgs. There is one N-MOSFET and P-MOSFET each for the
push pull output current limit control.

The circuit did not work out quite well by simulation. The current
limiting range is too small (300mA-800mA) and the positive and negative
current controll is not symetrical. Linearity is not good as well. I am
looking for some helps from this forum but did not get any luck to find
a hint by reading the articles there. Can somebody give me a hand out
there?


Thanks

-yan

 

[John Jardine.]

Hello experts,

I am working on a circuit that will amplify pulse signals to +/-45V
range to drive a capacitive load. The load is of a range that is less
than 5uF. The output buffer stage is BJT push pull pair class A. I am
having trouble to design a circuit that can limit the output current
within a range of 0-2A with 100mA step. Obviously the output current
limit should be controlable by a controlled voltage or current source,
but not hard coded by sensing resistor that control the Vbe of the
current limit BJT.

What I am doing right now is using a high CM input instrument amplifier
to isolate the voltage drop on the current limiting sensing resistor.
The REF input of the INA is connected with a controlled voltage source.
The output of the INA is then connected with the Gate of a MOSFET. The
MOSFET's D is connected to the base of BJT at the push pull out put
stage and the MOSFT's S is connected with the GND. By control the
voltage that is input into REF pin I can shift the INA's output, hence
to control the Vgs. There is one N-MOSFET and P-MOSFET each for the
push pull output current limit control.

The circuit did not work out quite well by simulation. The current
limiting range is too small (300mA-800mA) and the positive and negative
current controll is not symetrical. Linearity is not good as well. I am
looking for some helps from this forum but did not get any luck to find
a hint by reading the articles there. Can somebody give me a hand out
there?


Thanks

-yan

Sounds a bit messy. Can't you just put something like a 100mohm sense
resistor in the 0V return side of the load?. Wouldn't then need a diff amp.
john

 

[Michael]

Hello John,

Many thanks for your reply. Your suggestion is very smart, however in
this case the 0V side of the load is not accessable due to the load
itself (it is barried). Only a common gnd shared with several other
loads is exposed to my design.

Thanks again,

-yan

 

[[email protected]]

Hello experts,

I am working on a circuit that will amplify pulse signals to +/-45V
range to drive a capacitive load. The load is of a range that is less
than 5uF. The output buffer stage is BJT push pull pair class A. I am
having trouble to design a circuit that can limit the output current
within a range of 0-2A with 100mA step. Obviously the output current
limit should be controlable by a controlled voltage or current source,
but not hard coded by sensing resistor that control the Vbe of the
current limit BJT.

What I am doing right now is using a high CM input instrument amplifier
to isolate the voltage drop on the current limiting sensing resistor.
The REF input of the INA is connected with a controlled voltage source.
The output of the INA is then connected with the Gate of a MOSFET. The
MOSFET's D is connected to the base of BJT at the push pull out put
stage and the MOSFT's S is connected with the GND. By control the
voltage that is input into REF pin I can shift the INA's output, hence
to control the Vgs. There is one N-MOSFET and P-MOSFET each for the
push pull output current limit control.

The circuit did not work out quite well by simulation. The current
limiting range is too small (300mA-800mA) and the positive and negative
current controll is not symetrical. Linearity is not good as well. I am
looking for some helps from this forum but did not get any luck to find
a hint by reading the articles there. Can somebody give me a hand out
there?


Thanks

-yan

Yan,

I think that you have not provided enough details for the people here
to be able to give you many specific suggestions, unless maybe you just
want someone to suggest a different design. Perhaps you could post a
schematic of your circuit, somewhere, and provide a URL to it.

It sounds like you have identified several separate problem areas, in
your circuit. One problem is apparently in your BJTs' bases' driver
circuits. And you also can't get a large-enough range of currents.

Regarding the "output current range too small" problem: If you have
verified that the push-pull stage (with base driver stages), alone, can
produce a large-enough current-range, and you know what range of inputs
it needs, in order to do that, then the problem must be in your
current-sensing or input (to the base drivers) stage. (And, while
simulating the push-pull stage alone, you can also check to see if it
is contributing to your non-linearity and symmetry problems.)

Maybe you just need to multiply the inamp's output by a constant,
perhaps with a fixed-gain opamp amplifier, so that it will swing over a
larger range.

By the way: How do you tell the circuit what current it is supposed to
be producing? Your inamp apparently is giving you feedback, i.e. a
voltage corresponding to what current is actually being produced. Are
you *subtracting* that from a "desired output" input, to create the
control voltage for the input to the base drivers? Or does your input
to the inamp's REF input peform the equivalent task? (It seems like it
COULD. But, I don't have a clear picture of your circuit's topology.
However, if your pulses are +/- symmetrical, is it possible that simply
adding a REF voltage to the current-sense voltage could be contributing
to your output-symmetry problem?)

The inamp's REF input, if I recall correctly from the appnotes I've
read, is typically used to reference the inamp's output to a separate
ground level (although I'm sure it can be used in many other ways,
too).

For your circuit, it seems like you should simply be using your inamp's
(sensed feedback) output as the feedback for an opamp. The input of the
opamp would be your control voltage. The opamp's output would then be
used to generate your base drivers' inputs.

There are several good examples of push-pull "opamp current booster"
circuits in National Semiconductor's application note AN-272, at
http://www.national.com .

Good luck.

Regards,

Tom Gootee

 

[[email protected]]

Tom,

Sorry for confusing you guys. you can find the schematic here:

http://photos1.blogger.com/blogger/1908/3211/640/current limiter.jpg

You are right, the INA (instrument amp) is in the feed back loop. The
base is driven by a voltage source or an amplifier as it shows on the
drawing. Push pull stage needs to drive a signal of +/-45V and the
output current to the cap needs to be adjustabe between 0-2A with 100ma
step. The voltage source into the REF of ESS block (INA) will be set by
software through a DAC.

By the way, I will work on the input stage later, where I can use the
booster circuit you just pointed out. Many thanks from here. However
the circuits in AN272 can only achieve 35V and 3A max, the current is
good but the voltage range is kind shy in my application. do you have
any idea on how to improve the voltage swing to +/-45 on figure 8?
Maybe I can just use a higher rated transistor instead of 2N5880 (80Vce
on datasheet)?

Thanks

-yan

 

[Winfield Hill]

yw wrote...

I am working on a circuit that will amplify pulse signals to +/-45V
range to drive a capacitive load. The load is of a range that is less
than 5uF. The output buffer stage is BJT push pull pair class A. I am
having trouble to design a circuit that can limit the output current
within a range of 0-2A with 100mA step. Obviously the output current
limit should be controlable by a controlled voltage or current source,
but not hard coded by sensing resistor that control the Vbe of the
current limit BJT.

Rather than design a voltage amplifier with an external
voltage-programmable current limit, why not design a
voltage-to-current amplifier, i.e. voltage-programmable
current output, with an separate overall voltage-servo
control to subsequently turn it into a voltage amplifier.
For an example of a voltage-to-current amplifier circuit,
you can study one of my designs, here,
ftp://ftp.rowland.org/pub/hill/ris-496-1.pdf

Used in bridge mode, this amplifier can deliver up to
+/-250 volts at 0.5 amps. If I were to revisit this
design, I'd use complementary MOSFETs, instead of
Darlington output transistors, which suffer from
second breakdown. Although I designed a non-linear
foldback current limit to protect the output stage
from misuse, we still once suffered a BJT failure.

You'll notice the amplifier changes from current to
voltage mode at high frequencies (C13, C10 and R42),
which is necessary to deal with load inductance.

 

[Michael]

Win,

Thank you very much on your help. I went through the circuit and have
several points that I don't understand:


1. When you mentioned the overall voltage servo loop, were you saying
to construct a outside loop that enclose the current loop? but how do I
set the current limit? by stepping the voltage input at different size
of step? If so do you have any recommandation on choseing an op amp to
do the voltage loop? Is there anything like block diagram that I can
work with?
2. This circuit is working at less than 700mA current limit. In my
application the supply will only be +/-50V, I checked the data sheet,
looks like I can I increase the max current limit to 2A, can I?
3. I don't see how the out put of U6 coupled with the following stage.
can you give me a hint on how the input signal get to the rest of the
circuit?
4. I Only see a gain of 1 on the U6 amplifier circuit. What if I
increase the gain by changing the value of R36 and R37?
5. The load I am now facing is a huge capacitive load ( can be up to
18uF), currently I am working on a typical load of 4.8uF, is there any
thing I need to be careful with under such load situation?, such as
stabilities.
6. I am new to this area, I have the book you wrote "the art of
electronics". Besides that is there any other reading that you
recommand?

Thanks

-yan

 

[Winfield Hill]

Michael wrote...

Thank you very much on your help. I went through the circuit and
have several points that I don't understand:


1. When you mentioned the overall voltage servo loop, were you saying
to construct a outside loop that enclose the current loop? but how do
I set the current limit?

That can be set by a voltage input to the circuit I referenced.

If so do you have any recommandation on choseing an op amp to
do the voltage loop? Is there anything like block diagram that I can
work with?

I imagine you're imagining an amplifier with two control inputs,
one each for voltage and current limits. A transconductance
opamp, like the venerable CA3080, placed external to the current
amplifier easily can do the task, because it has an input to set
the maximum current (with which it will drive the power current
amplifier) and a summing-junction opamp input you can use for
the voltage feedback. Sadly, the CA3080 and NSC's LM3080 copy
have nearly disappeared, but DigiKey stocks the LM13700 dual,
http://www.digikey.com/scripts/dksearch/dksus.dll?Pname?Name=LM13700N-ND

2. This circuit is working at less than 700mA current limit. In my
application the supply will only be +/-50V, I checked the data sheet,
looks like I can I increase the max current limit to 2A, can I?

Yes, and change part values all over the place as appropriate.

3. I don't see how the output of U6 coupled with the following stage.
can you give me a hint on how the input signal get to the rest of the
circuit?

By means of U6's supply current, as determined by the load on
the output of U6, and its servo'd output voltage. You could
write out the formulas, or just mentally analyze the operation.
An easy way to understand it is to start with the opamp output
at zero, and observe that the opamp's operating current, plus a
little current from R19, is the input to the gain-of-200 current
mirrors on the HV supply rails. This gives the power transistors
a class-A operating current, but the net output current is zero.
If the opamp's output moves away from zero volts, an unbalanced
current is created by R25 and appears at the output 200x larger.

4. I Only see a gain of 1 on the U6 amplifier circuit. What
if I increase the gain by changing the value of R36 and R37?

That's the overall servo gain to the voltage or current-monitor
opamps. Their attenuated signal from the output or from the
current-monitor circuits determines the final amplifier gain.

5. The load I am now facing is a huge capacitive load ( can be
up to 18uF), currently I am working on a typical load of 4.8uF,
is there any thing I need to be careful with under such load
situation?, such as stabilities.

This type of amplifier is basically a power transconductance
amp, which means its open-loop voltage gain is gm * X_load,
which drops proportional to frequency for large capacitive loads.
In such a circuit, we use components like C13 to stabilize the
amp by providing a feedback zero to cancel the cap-load pole.

6. I am new to this area, I have the book you wrote "the art
of electronics". Besides that is there any other reading that
you recommand?

Tony Williams and I have written about this type of amplifier
several times in threads on s.e.d. There are also a few app
notes by NSC and perhaps LTC. I don't remember writing much
about it in AoE, although there may be a short mention.

 

[Tony Williams]

[/QUOTE]

Tony Williams and I have written about this type of amplifier
several times in threads on s.e.d. There are also a few app
notes by NSC and perhaps LTC. I don't remember writing much
about it in AoE, although there may be a short mention.

I remember that there were two little design points
on that circuit of yours that I admired most.

Firstly, knowing beforehand how to choose the topology
and values for R25/C9 in order to form a Zobel network
with the output impedance of the AD545. I had to do it
by the suck-it-and-see method. Secondly, that crafty
way of nicking the power supplies for the U5/U8 current
monitors.

 

[Michael]

Hello Win,

Further questions on the design,

By means of U6's supply current, as determined by the load on
the output of U6, and its servo'd output voltage. You could
write out the formulas, or just mentally analyze the operation.
An easy way to understand it is to start with the opamp output
at zero, and observe that the opamp's operating current, plus a
little current from R19, is the input to the gain-of-200 current
mirrors on the HV supply rails. This gives the power transistors
a class-A operating current, but the net output current is zero.
If the opamp's output moves away from zero volts, an unbalanced
current is created by R25 and appears at the output 200x larger.

Question:

Since the unbalanced current presents on R25 could be the offset of U6,
does that mean I can expect 200xlarger offset current presents at the
output stage?In my design the DC accuracy is more important, how can I
minimize in my design.

This type of amplifier is basically a power transconductance
amp, which means its open-loop voltage gain is gm * X_load,
which drops proportional to frequency for large capacitive loads.
In such a circuit, we use components like C13 to stabilize the
amp by providing a feedback zero to cancel the cap-load pole.

Question:
You have already inluded a feedback zero in the crrent loop within the
design, add another feed back zero like this in the "outside servo
voltage loop" will be redundent, isn't that right? Also since C9 is in
place to stablized the circuit, playing with C9's value would help as
well? Is there a good way to determine C9's best value?

More Questions:

1. R6 and L1 pluss C5 and R3 are impedance match network I guess is
originally designed for inductive load of a speaker coil. In my
application the load is pure capacitive and resistive. Keep this
network in place will do any good?

2. What is the purpose of R43 that connect between AGND and HV-common?

Thank you very much

-yan

 

[Winfield Hill]

Michael wrote...

Hello Win,

Further questions on the design,
ftp://ftp.rowland.org/pub/hill/ris-496-1.pdf


Question:

Since the unbalanced current presents on R25 could be the offset of
U6, does that mean I can expect 200xlarger offset current presents
at the output stage?In my design the DC accuracy is more important,
how can I minimize in my design.

Not exactly. The opamp offset error works against the signal
from the current-monitor opamps U7 and U1A. They work with
the current signal developed across R29. And R29 works with
the supposedly-identical class-A currents through Darlington
power transistors U3 and U4, as reported by U5 and U8 with
their offset voltages. So there's a class-A current reported
with say 1% error, and IIRC this becomes the dominant output-
current offset error. My memory is this is fairly small, but
I'd better check before making any assertions.

Question:
You have already inluded a feedback zero in the crrent loop within
the design, add another feedback zero like this in the "outside
servo voltage loop" will be redundent, isn't that right?
No.

Also since C9 is in place to stablized the circuit, playing with
C9's value would help as well? Is there a good way to determine
C9's best value?

Tony says I had a good way to do this, and he may be right. As
it stands the R25 C9 zero is at 107kHz, whereas the overall gain
response rolls off given by R37 C13 at 48kHz. So it appears the
zero is well positioned to help cancel any pole causing trouble
with the loop's unity-gain frequency phase margin.

The issue of a capacitive output load is dealt with elsewhere.

More Questions:

1. R6 and L1 pluss C5 and R3 are impedance match network I guess
is originally designed for inductive load of a speaker coil.

No, that's just where you're used to seeing it. Capacitve loads
come with many applications, and this type of netowrk isolates
the feedback loop from their problems above a certain frequency.

In my application the load is pure capacitive and resistive.
Keep this network in place will do any good?

Possibly, what's your bandwidth requirement when driving huge
5 to 20uF capacitive loads? What's your slew-rate requirement?

2. What is the purpose of R43 that connect between AGND and
HV-common?

That allows the high-power high-voltage supply to be isolated
from the low-noise analog opamp supply, and provides a dc link.

Thank you very much

You're welcome, yan, you asked good questions.

 

[Michael]

Hello Win,

Possibly, what's your bandwidth requirement when driving huge
5 to 20uF capacitive loads? What's your slew-rate requirement?

In this situation the current will be limited at 2A at the maximum.
Therefore the slew rate for an load at 5u, we can only expect 0.4V/us
slew rate based on i=c*dv/dt. for 20uF the slew rate will decline to
0.1v/us due to the current limit. And that is what I wrote on the spec.
However some time the load is at the range of less than 600nF, at that
range we will have 4V/us slew rate at around 2A charging current.

Following your suggestion, I just build a quick model trying to
verifying the idea of using LM13700. The circuit is posted here at:

http://photos1.blogger.com/blogger/1908/3211/640/LM13700_MODEL.jpg

I had difficulties to make the model working properly. Actually by
adjusting I_ABC, I changed the gm, hence the open_loop gain. I was not
able to observe the current from LM13700 changing. Also I noticed an
offset of almost 2V and the output. Something wrong on the model? I
used a simplified ABM to mimic the high power stage and voltage
feedback.

Linear has a VFB operational amplifier with output current limiting of
+/-500mA, LT1970, will this one do a better job in this case? It is
much more expensive.

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1028,P2179,D3840

Thanks,

-yan

 

[Winfield Hill]

Michael wrote...

Following your suggestion, I just build a quick model trying to
verifying the idea of using LM13700. The circuit is posted here at:
http://photos1.blogger.com/blogger/1908/3211/640/LM13700_MODEL.jpg

I had difficulties to make the model working properly. ...

When using a current-programmable transconductance amplifier
you certainly don't want to add an output buffer because
that destroys its properties. I was suggesting one as an
input to the SJ of my circuit, and adding the accessory EF
disables the feature we were looking for.

Linear has a VFB operational amplifier with output current limiting
of +/-500mA, LT1970, will this one do a better job in this case?
It is much more expensive.
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1028,P2179,D3840

Expensive, Smnensive. Actually that's a cool part: thanks
for pointing it out, I hadn't seen it before. There's lots
you could do with that little $10 beast, either directly, or
indirectly with outlying circuits for more voltage or power.

 

[Michael]

Hello Win,

Again thank you very much for you quick reply. I have made some
progresses on this project because of the helps from you and others in
this forum. I really appreciate it.

I tried the Linear chip this afternoon and it works fine on the model
simulation. But it is too expensive. I still want to try LM13700 out on
this design.

Actuallly, before I sent you the email earlier today, the first thing I
tried out on LM13700 is by using its non-buffered output. The signal
was coupled to the 10V/A current loop ABM through a resistive load
resistor. Still it did not work out. Tomorrow I plan to spend more time
on this try to make it work. Maybe you can help me out when you get a
chance.

When using a current-programmable transconductance amplifier
you certainly don't want to add an output buffer because
that destroys its properties. I was suggesting one as an
input to the SJ of my circuit, and adding the accessory EF
disables the feature we were looking for.

Can you explain what "SJ" means?
Also, can you tell me the offset and noise distribution of your
circuit?

Thanks,

-yan

 

[Fred Bloggs]

I am working on a circuit that will amplify pulse signals to +/-45V
range to drive a capacitive load. The load is of a range that is less
than 5uF. The output buffer stage is BJT push pull pair class A. I am
having trouble to design a circuit that can limit the output current
within a range of 0-2A with 100mA step. Obviously the output current
limit should be controlable by a controlled voltage or current source,
but not hard coded by sensing resistor that control the Vbe of the
current limit BJT.

Is that all your circuit is supposed to do: fixed +/-45V ( no 0V
quiescent-just a simple two-state) into capacitive load ( negligible
resistance), current limiting the output over range of 0-2A in 0.1A
increments, no duty limitations either large or small, burst mode,
maximum pulse train frequency? As it stands, your description of
requirements is way too vague, try describing the "whole circuit" or
"black box" description of its intended function. You people who come on
here with your dammed *abstractions* of *what YOU think* is the crux of
the circuit requirement always get screwed, and you do this to yourselves.