If you are making [a] multiplying PLL and have a lowpass before the
comparitor...
Terminology, please. Is a multiplying PLL a clock-multiplying PLL? Or
do you mean a multiplying phase detector, mentioned earlier? The
fed-back sawtooth does which?
Ok, I'll try to be clear, although this is a Monday:
Assume you have a VCO running at several times the input frequency. ie: a
"multiplying PLL".
It is a fairly easy matter to filter the input signal so that it has no
components above some fraction of the VCO's frequency. The filter really
should remove the 3rd harmonic of the expected frequency and above.
The VCO's output can be made into a (not super good) sawtooth with a
simple low pass filter.
If the input signal is connected to one input of a comparitor and the
other side of the comparitor is driven with a scaled version of the
sawtooth, you get a PWMed output from the comparitor. If the sawtooth's
amplitude is adjusted so that it is just a little bigger than the biggest
signal, the PWM doesn't saturate.
Now when this PWM train goes through the XOR, you get a bunch of
frequencies on the output of the XOR.
(a) The frequency content of the input multiplied by the fundamental of
the "feedback" signal of the PLL. This is the signal that you want for
making the PLL track the input.
(b) The frequency contents of the input signal multiplied by the
harmonics of the "feedback" signal. This is unwanted and the loop filter
on the PLL usually will remove it.
(c) The PWM frequency and its harmonics. This is another unwanted signal
that gets eaten up by the loop filter.
(d) The PWM frequency and its harmonics intermixed with the harmonics of
the "feedback" signal. Assuming that the feedback signal is 50-50 duty
cycle and that the VCO is running at 2^N times the feedback, all of the
energy in this also ends up at high frequencies. This also gets eaten by
the loop filter.