Hi all.
I have a voltage divider connected to a PIC I/O line. A pulse comes in at the top of the divider network, scaled downand fed into the PIC. I am inly detecting for a high to low edge usibg interrupts.
This happens only once a day for 4ms then off.
I am finding that i am getting a current draw of 50uA when in the idle state. It is from the PIC to the bottom resistor of the divider to 0V.
When i check my pulse, i make the port as an input. Should i make this as a output driven low when i am not checking for my pulse train or tri state to avoid current drain?
Please could soneone explain what happens internally to the PIC lines at FET level too. I presume we have n and p type FETs to sink and source current through the I/O line.
Thanks in advance
I have a voltage divider connected to a PIC I/O line. A pulse comes in at the top of the divider network, scaled downand fed into the PIC. I am inly detecting for a high to low edge usibg interrupts.
This happens only once a day for 4ms then off.
I am finding that i am getting a current draw of 50uA when in the idle state. It is from the PIC to the bottom resistor of the divider to 0V.
When i check my pulse, i make the port as an input. Should i make this as a output driven low when i am not checking for my pulse train or tri state to avoid current drain?
Please could soneone explain what happens internally to the PIC lines at FET level too. I presume we have n and p type FETs to sink and source current through the I/O line.
Thanks in advance