Phase Locked Loop Phase Shift

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Hi All,

I'm trying to design a PLL frequency multiplier which will track a
50Hz +- 1Hz sinusoidal signal and generate a clock at a rate of
12.8Khz nominal, synchronised to that signal. (*256 multiplication)

I've got an LM565 phase locked loop and have built a circuit which has
a divide by 256 counter in the feedback loop, similar to the reference
design on page 7 of the datasheet (http://cache.national.com/ds/LM/
LM565.pdf) albeit with different component values and a lead lag
filter .

This circuit works to a point - I've succesfully locked onto the input
signal and am generating a 12.8khz clock which is synchronised to the
input waveform.

However, as I vary the input frequency between 49 and 51hz, there is a
change in phase between the output and the input which can be clearly
seen by comparing pins 2 (input) and 5 (divided signal - input to the
phase detector.)

Someone has said that this is because the LM565 has a type one phase
detector (?) and hence there will always be a phase error which is
dependent on input frequency - is that correct?

For reference, the parameters of the loop are as follows....

Free running frequency - 12.8khz (hand tuned)
Loop Gain 86016 (from datasheet)
Natural Frequency 864hz
Damping factor 1.39
T1 cutoff frequency - 8.45
T2 cutoff frequency - 312.5

If anyone could offer any advice, then I'd be most grateful.

Thanks,

Jim

 

[John Popelish]

However, as I vary the input frequency between 49 and 51hz, there is a
change in phase between the output and the input which can be clearly
seen by comparing pins 2 (input) and 5 (divided signal - input to the
phase detector.)

Someone has said that this is because the LM565 has a type one phase
detector (?) and hence there will always be a phase error which is
dependent on input frequency - is that correct?

For reference, the parameters of the loop are as follows....

Free running frequency - 12.8khz (hand tuned)
Loop Gain 86016 (from datasheet)
Natural Frequency 864hz
Damping factor 1.39
T1 cutoff frequency - 8.45
T2 cutoff frequency - 312.5

If anyone could offer any advice, then I'd be most grateful.

The DC control voltage sent to the voltage controlled
oscillator is proportional to the phase error, so changing
the oscillator frequency requires a change in the phase
error. Add an integrator in that control loop and the phase
error will be fixed over the frequency range. Or switch to
a CD4046 type PLL chip that has a form of integrator
included as a second choice of phase detector and get a zero
phase error between the reference and the divider output.

 

[Phil Hobbs]

Hi All,

I'm trying to design a PLL frequency multiplier which will track a
50Hz +- 1Hz sinusoidal signal and generate a clock at a rate of
12.8Khz nominal, synchronised to that signal. (*256 multiplication)

I've got an LM565 phase locked loop and have built a circuit which has
a divide by 256 counter in the feedback loop, similar to the reference
design on page 7 of the datasheet (http://cache.national.com/ds/LM/
LM565.pdf) albeit with different component values and a lead lag
filter .

This circuit works to a point - I've succesfully locked onto the input
signal and am generating a 12.8khz clock which is synchronised to the
input waveform.

However, as I vary the input frequency between 49 and 51hz, there is a
change in phase between the output and the input which can be clearly
seen by comparing pins 2 (input) and 5 (divided signal - input to the
phase detector.)

Someone has said that this is because the LM565 has a type one phase
detector (?) and hence there will always be a phase error which is
dependent on input frequency - is that correct?

For reference, the parameters of the loop are as follows....

Free running frequency - 12.8khz (hand tuned)
Loop Gain 86016 (from datasheet)
Natural Frequency 864hz
Damping factor 1.39
T1 cutoff frequency - 8.45
T2 cutoff frequency - 312.5

If anyone could offer any advice, then I'd be most grateful.

Thanks,

Jim

It isn't the multiplying phase detector that's at fault, it's low loop
gain. In order for the VCO to go from 49 to 51 Hz, its control voltage
has to move a little bit:

delta V = delta f/(df_vco/dV)

If there isn't much gain between the phase detector and the VCO, the
phase shift has to change in order to generate that delta V. This is
true regardless of what kind of phase detector you're using.

If you put an op amp between the phase detector and VCO--with an
appropriate lead/lag network so the loop doesn't become unstable--you
can get rid of the phase error by a factor of about a million.

Cheers,

Phil Hobbs

 

[Jamie]

Hi All,

I'm trying to design a PLL frequency multiplier which will track a
50Hz +- 1Hz sinusoidal signal and generate a clock at a rate of
12.8Khz nominal, synchronised to that signal. (*256 multiplication)

I've got an LM565 phase locked loop and have built a circuit which has
a divide by 256 counter in the feedback loop, similar to the reference
design on page 7 of the datasheet (http://cache.national.com/ds/LM/
LM565.pdf) albeit with different component values and a lead lag
filter .

This circuit works to a point - I've succesfully locked onto the input
signal and am generating a 12.8khz clock which is synchronised to the
input waveform.

However, as I vary the input frequency between 49 and 51hz, there is a
change in phase between the output and the input which can be clearly
seen by comparing pins 2 (input) and 5 (divided signal - input to the
phase detector.)

Someone has said that this is because the LM565 has a type one phase
detector (?) and hence there will always be a phase error which is
dependent on input frequency - is that correct?

For reference, the parameters of the loop are as follows....

Free running frequency - 12.8khz (hand tuned)
Loop Gain 86016 (from datasheet)
Natural Frequency 864hz
Damping factor 1.39
T1 cutoff frequency - 8.45
T2 cutoff frequency - 312.5

If anyone could offer any advice, then I'd be most grateful.

Thanks,

Jim

http://www.maxim-ic.com/appnotes.cfm/an_pk/1130

Check that one out, it's designed to provide minimum pulse
width a the detector to prevent dead band problems witch is
part of your phase shift issue.

 

[Tom Del Rosso]

Or switch to
a CD4046 type PLL chip that has a form of integrator
included as a second choice of phase detector and get a zero
phase error between the reference and the divider output.

Which of its detectors are you refering to there?

 

[John Popelish]

Which of its detectors are you refering to there?

I am talking about phase detector II, the one that goes open
circuit when zero phase error is reached, and if used to
drive a filter that has no resistor across it (typically a
resistor in series with a capacitor or a series RC in
parallel with another capacitor), will hold its voltage with
no further error signal.