Deepthi said:
I am trying to analyse the working of a conventional phase frequency
detector(NAND based).I would like to know why the deadzone is high for
it specially when the reset delay is large.Please could anyone help me
out with it atleast an article.
If you mean a three-state phase detector with "up", "down" and
"middling" outputs, the usual cause of a deadzone is because of
metastability. The basic construction of the phase detector uses two
clocks, so both latches can go off at the same time (giving you
simultaneous up and down). There's a circuit that detects this and
resets both latches, but it's subject to metastability. Since the
target operating point of the usual PLL is to be right at he point of
simultaneous clocking you're just asking for trouble.
Motorola advertises "special circuitry" to minimize this metastability.
IIRC they're pretty vague about exactly how they do it. Phillips uses
some sort of clever pulse-absorption circuit that causes the PLL set
point to be about 10% away from the danger zone -- it's in their
synthesizer data sheets.