P-channel MOSFET gate-source diode

[Robert Scott]

Suppose I have a P-channel enhancement mode MOSFET set up for high-side
switching (Source=positive rail, Drain=load to ground). I know that when the
gate is sufficiently more negative than the source, then the FET will conduct.
But my quesiton is about what happens when the FET is supposed to be off.
Specifically, what happens if the Gate is biased a few volts more positive than
the source? That forward-biases the internal Gate-Source diode, and some
current flows there. But is it safe to say that none of that current flows to
the drain? For my application it is important that there be essentially no
drain current, even if the gate is biased more positive than the source.

 

[Jim Thompson]

Suppose I have a P-channel enhancement mode MOSFET set up for high-side
switching (Source=positive rail, Drain=load to ground). I know that when the
gate is sufficiently more negative than the source, then the FET will conduct.
But my quesiton is about what happens when the FET is supposed to be off.
Specifically, what happens if the Gate is biased a few volts more positive than
the source? That forward-biases the internal Gate-Source diode, and some
current flows there.

Eh? MOS Devices don't have a gate-source diode, only JFET's do. An
MOS gate is a capacitor.

But is it safe to say that none of that current flows to
the drain? For my application it is important that there be essentially no
drain current, even if the gate is biased more positive than the source.

...Jim Thompson
--
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Lord protect me from fascists, perverts and Democrats

 

[Robert Scott]

Eh? MOS Devices don't have a gate-source diode, only JFET's do. An
MOS gate is a capacitor.

Good. I guess I was extrapolating from JFETs. An yes, John Larkin, I will be
limiting the current with 100K anyway. So thanks to both of you, I will proceed
with the design.


Robert Scott
Ypsilanti, Michigan

 

[Jamie]

Suppose I have a P-channel enhancement mode MOSFET set up for high-side
switching (Source=positive rail, Drain=load to ground). I know that when the
gate is sufficiently more negative than the source, then the FET will conduct.
But my quesiton is about what happens when the FET is supposed to be off.
Specifically, what happens if the Gate is biased a few volts more positive than
the source? That forward-biases the internal Gate-Source diode, and some
current flows there. But is it safe to say that none of that current flows to
the drain? For my application it is important that there be essentially no
drain current, even if the gate is biased more positive than the source.

Why don't you look up the spec sheet for it.

It tells you the leakage in the off state.

I can tell you that it's very low.

Also beware of body diodes some varieties.