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Op Amp Stability
- Thread starter Arouse1973
- Start date
Thank you - normally, I also have a sense of humour
Arouse1973
Adam
I have tried to answer Lvw's questions to the best of my ability, here they are. I have not included wording changes request by Lvw.
1)Thread Quote:
This gain is usually very high. It is high because you normally close the loop with feedback which stabilises the op-amp and increases the bandwidth of the op-amp.
LVW Said:
Feedback stabilizes the DC operating point only. Dynamic stability is degraded ! The bandwidth of the opamp unit remains unchanged. However, the closed-loop bandwidth of the amplifier with feedback is larger than the open-loop bandwidth.
Answer from Adam:
I was under the impression that when you use negative feedback this reduces the gain uncertainty of the op-amp which in open loop can have quite a high tolerance between the same types of op-amps. Also I thought negative feedback reduced output impedance and increased input impedance. The reduction in output impedance will allow the op-amp to drive higher capacitive loads than when in open loop configuration and the increased input impedance limits the loading on the source driving it. So that’s why I used the word stabilise. Maybe I need to use a different term?
2)Thread Quote:
This is important because if this product ever equals -1 which is -1 <–180 ˚phase shift the circuit could oscillate.
LVW Said:
This is in contrast to Fig. 6a, 6b, Fig. 7 and 9 (phase margin against 0 deg). This results from the confusion regarding the definition of loop gain (with/without sign inversion) .
Answer from Adam:
Sorry I don’t quite understand this point can you please clarify what you mean. Can you suggest better wording or should it be removed.
3)Thread Quote:
It’s interesting to note that a reduction in frequency of 10 times fc reduces the phase to -5.7˚and an increase takes the phase to -84.3˚.
LVW Said:
What is fc? Why is it interesting to know about the mentioned phase changes?
Answer from Adam:
Fc is the cut off frequency the point where the output has fallen 3dB from the original input signal. I understood that -5.7˚ was the point at which it is accepted that attenuation starts, all though I suppose it starts from any signal that’s not d.c. I understood the -84.3˚is the accepted stop band which is 10 times the frequency this adds up to -90 degrees the maximum phase shift a single pole response can give. Is this correct?
3)Thread Quote:
It means I require gain now to be within the safe limit. But look what is has done to my bandwidth, reduced it to about 25KHz.
LVW Said:
This is not clear to me. Why do you require „more gain“? Which graph shows the 25 kHz bandwidth?
Answer from Adam:
Yes this is incorrect for the stated plot and its 45 KHz not 25 KHz. I think I intended to use a unity gain buffer originally and I was thinking of adding gain to this to improve the circuit’s performance. It will be removed.
4)Thread Quote:
Well because of the op-amp input capacitance causing a pole with the source impedance you will only get 180˚ at d.c.
Lvw Said:
No. The 180deg phase shift simply results from the inverting input.
Answer from Adam:
I understand that to achieve exactly 180˚from the start the input would have to be d.c and because the input is a sine wave you will always have a phase shift although at very low frequencies it is very small. Is this correct?
5)Thread Quote:
Let’s look at an inverting amplifier with a gain of 10. Now we have closed the loop how do we tell if our system is still stable? We have to compare open loop gain where it meets the Vout/Vin gain line.
Why? This is not correct. The only gain that matters is the loop gain Aol*beta. Thus, we have to see where Aol*beta=1, which means Aol=1/beta. Hence: Where is Aol crossing 1/beta?
Answer from Adam:
Yes this will be reworded.
6)Thread Quote:
Or plot aol × 1/11 which is open loop multiplied but 1/gain which remember has to be 11 now.
LVW Said:
Yes - it is correct: Loop gain=Aol*beta=Aol*1/11. However, the gain was -10 (not 11)
Answer from Adam:
I don’t quite understand what you mean -10
7)Thread Quote:
Where the Aol and Vout/Vin (gain) lines meet before the gain rolls off gives a phase margin of approx. 85˚so we are still stable although
LVW Said:
No - the phase margin is determined where the loop gain crosses the 0dB line (Fig. 6a and 6b). I can see no graph where both gain „lines meet“.
Answer from Adam:
That part needs removing. The wording remained from an older plot.
8)Thread Quote:
Now it is only the loop delay that is measured and you will notice I had to add gain to the chart in figure 6 because the new method gives a gain of 11.
LVW Said:
Why do you speak about loop delay? Delay is never measured or simulated. Why adding gain? Which gain is „11“? Why?
Answer from Adam:
Don’t know why I said that, it makes no sense, I’ll remove it. Because the in loop method gives a gain of 11 I had to add a gain of one to the non loop simulation measurement I was making on a non inverting amplifier which had a gain of 10 originally, I needed to make the gains the same so the results matched.
9)Thread Quote:
If the loop gain reaches -1 we have an unstable op-amp circuit.
LVW Said:
The phase margin with a load capacitance of 20nF was shown to be 27deg. Therefore, what is the meaning of the above sentence? The circuit is stable!
Answer from Adam:
Maybe I need to reword this and add something about minimum phase margin is considered to be 45˚although technically the circuit is still stable with a phase margin of 27˚
10)Thread Quote:
A reference buffer that is unstable because of too large a resistance on the input which causes increase loop delay due internal and external capacitances and of course causes a reduction in phase margin.
LVW Said:
No - the input resistance does not degrade stability (By the way: What is the purpose of R8 and R9 ?) . We have instability because of 100% feedback (most critical case) together with an extremely large load capacitor
Answer from Adam:
The input capacitance and large input resistance can cause ringing. Is ringing not classed as a stability issue? R8 and R9 are there to show an example of a circuit that will cause oscillation on start up. The circuit is a poor voltage reference.
11)Thread Quote:
This is what happens with an amplifier with a gain of 10. Circuit driven with 0.01V 50Hz varying D.C waveform.
LVW Said:
Why not saying : AC signal with 50Hz ?
Answer from Adam:
It goes from 0V to maximum not to a minus voltage, so it’s varying d.c isn’t it?.
LVW Said:
Comments/questions to Fig. 17 and 18:
*What is the purpose of C1 in Fig. 18?
*This capacitor C1 heavily degrades stability (makes the circuit unstable).
*As a consequence, Fig. 17 is meaningless because AC analysis of unstable circuits give no meaningful results, see the plotted gain of 8 dB (for a circuit that should give 20 dB gain).
Answer from Adam:
This shows what happens if someone thinks of filtering the input with a capacitor. It is suppose to show instability. Surely a.c analysis shows whether a circuit is stable or not otherwise why measure phase margin in the first place?
I still need to go through and add some more amendment as requested.
Thanks
Adam
1)Thread Quote:
This gain is usually very high. It is high because you normally close the loop with feedback which stabilises the op-amp and increases the bandwidth of the op-amp.
LVW Said:
Feedback stabilizes the DC operating point only. Dynamic stability is degraded ! The bandwidth of the opamp unit remains unchanged. However, the closed-loop bandwidth of the amplifier with feedback is larger than the open-loop bandwidth.
Answer from Adam:
I was under the impression that when you use negative feedback this reduces the gain uncertainty of the op-amp which in open loop can have quite a high tolerance between the same types of op-amps. Also I thought negative feedback reduced output impedance and increased input impedance. The reduction in output impedance will allow the op-amp to drive higher capacitive loads than when in open loop configuration and the increased input impedance limits the loading on the source driving it. So that’s why I used the word stabilise. Maybe I need to use a different term?
2)Thread Quote:
This is important because if this product ever equals -1 which is -1 <–180 ˚phase shift the circuit could oscillate.
LVW Said:
This is in contrast to Fig. 6a, 6b, Fig. 7 and 9 (phase margin against 0 deg). This results from the confusion regarding the definition of loop gain (with/without sign inversion) .
Answer from Adam:
Sorry I don’t quite understand this point can you please clarify what you mean. Can you suggest better wording or should it be removed.
3)Thread Quote:
It’s interesting to note that a reduction in frequency of 10 times fc reduces the phase to -5.7˚and an increase takes the phase to -84.3˚.
LVW Said:
What is fc? Why is it interesting to know about the mentioned phase changes?
Answer from Adam:
Fc is the cut off frequency the point where the output has fallen 3dB from the original input signal. I understood that -5.7˚ was the point at which it is accepted that attenuation starts, all though I suppose it starts from any signal that’s not d.c. I understood the -84.3˚is the accepted stop band which is 10 times the frequency this adds up to -90 degrees the maximum phase shift a single pole response can give. Is this correct?
3)Thread Quote:
It means I require gain now to be within the safe limit. But look what is has done to my bandwidth, reduced it to about 25KHz.
LVW Said:
This is not clear to me. Why do you require „more gain“? Which graph shows the 25 kHz bandwidth?
Answer from Adam:
Yes this is incorrect for the stated plot and its 45 KHz not 25 KHz. I think I intended to use a unity gain buffer originally and I was thinking of adding gain to this to improve the circuit’s performance. It will be removed.
4)Thread Quote:
Well because of the op-amp input capacitance causing a pole with the source impedance you will only get 180˚ at d.c.
Lvw Said:
No. The 180deg phase shift simply results from the inverting input.
Answer from Adam:
I understand that to achieve exactly 180˚from the start the input would have to be d.c and because the input is a sine wave you will always have a phase shift although at very low frequencies it is very small. Is this correct?
5)Thread Quote:
Let’s look at an inverting amplifier with a gain of 10. Now we have closed the loop how do we tell if our system is still stable? We have to compare open loop gain where it meets the Vout/Vin gain line.
Why? This is not correct. The only gain that matters is the loop gain Aol*beta. Thus, we have to see where Aol*beta=1, which means Aol=1/beta. Hence: Where is Aol crossing 1/beta?
Answer from Adam:
Yes this will be reworded.
6)Thread Quote:
Or plot aol × 1/11 which is open loop multiplied but 1/gain which remember has to be 11 now.
LVW Said:
Yes - it is correct: Loop gain=Aol*beta=Aol*1/11. However, the gain was -10 (not 11)
Answer from Adam:
I don’t quite understand what you mean -10
7)Thread Quote:
Where the Aol and Vout/Vin (gain) lines meet before the gain rolls off gives a phase margin of approx. 85˚so we are still stable although
LVW Said:
No - the phase margin is determined where the loop gain crosses the 0dB line (Fig. 6a and 6b). I can see no graph where both gain „lines meet“.
Answer from Adam:
That part needs removing. The wording remained from an older plot.
8)Thread Quote:
Now it is only the loop delay that is measured and you will notice I had to add gain to the chart in figure 6 because the new method gives a gain of 11.
LVW Said:
Why do you speak about loop delay? Delay is never measured or simulated. Why adding gain? Which gain is „11“? Why?
Answer from Adam:
Don’t know why I said that, it makes no sense, I’ll remove it. Because the in loop method gives a gain of 11 I had to add a gain of one to the non loop simulation measurement I was making on a non inverting amplifier which had a gain of 10 originally, I needed to make the gains the same so the results matched.
9)Thread Quote:
If the loop gain reaches -1 we have an unstable op-amp circuit.
LVW Said:
The phase margin with a load capacitance of 20nF was shown to be 27deg. Therefore, what is the meaning of the above sentence? The circuit is stable!
Answer from Adam:
Maybe I need to reword this and add something about minimum phase margin is considered to be 45˚although technically the circuit is still stable with a phase margin of 27˚
10)Thread Quote:
A reference buffer that is unstable because of too large a resistance on the input which causes increase loop delay due internal and external capacitances and of course causes a reduction in phase margin.
LVW Said:
No - the input resistance does not degrade stability (By the way: What is the purpose of R8 and R9 ?) . We have instability because of 100% feedback (most critical case) together with an extremely large load capacitor
Answer from Adam:
The input capacitance and large input resistance can cause ringing. Is ringing not classed as a stability issue? R8 and R9 are there to show an example of a circuit that will cause oscillation on start up. The circuit is a poor voltage reference.
11)Thread Quote:
This is what happens with an amplifier with a gain of 10. Circuit driven with 0.01V 50Hz varying D.C waveform.
LVW Said:
Why not saying : AC signal with 50Hz ?
Answer from Adam:
It goes from 0V to maximum not to a minus voltage, so it’s varying d.c isn’t it?.
LVW Said:
Comments/questions to Fig. 17 and 18:
*What is the purpose of C1 in Fig. 18?
*This capacitor C1 heavily degrades stability (makes the circuit unstable).
*As a consequence, Fig. 17 is meaningless because AC analysis of unstable circuits give no meaningful results, see the plotted gain of 8 dB (for a circuit that should give 20 dB gain).
Answer from Adam:
This shows what happens if someone thinks of filtering the input with a capacitor. It is suppose to show instability. Surely a.c analysis shows whether a circuit is stable or not otherwise why measure phase margin in the first place?
I still need to go through and add some more amendment as requested.
Thanks
Adam
Hi Adam,
at first, a general remark to my questions: By asking "why?" I could - in most cases - imagine what you mean (for example: fc) - however, I thought it would be necessary for the reader (newcomer) to know the definition. In general, I think no symbol or abbreviation should be used in any text without a corresponding definition.
Some comments from my side follow:
Answer from Adam:
I was under the impression that when you use negative feedback this reduces the gain uncertainty of the op-amp which in open loop can have quite a high tolerance between the same types of op-amps. Also I thought negative feedback reduced output impedance and increased input impedance. The reduction in output impedance will allow the op-amp to drive higher capacitive loads than when in open loop configuration and the increased input impedance limits the loading on the source driving it. So that’s why I used the word stabilise. Maybe I need to use a different term?
In short: We apply negative feedback to fix/stabilize a DC operating point (like in transistor amplifiers).
At the same time, this is connected with additinal advantages: Increase of input resistance (only non-inverter) , decrease of output resistance, closed-loop gain practically determined by external resistors only, closed-loop bandwidth increase.
However, in electronics each parameter improvement is connected with a degradation of another parameter - in our case: Degradation of dynamic stabilty (stability margin is inversely proportional to the feedback factor). This is demonstrated with the help of loop gain analyses (Nyquist stability criterion).
This is important because if this product ever equals -1 which is -1 <–180 ˚phase shift the circuit could oscillate.
LVW Said:
This is in contrast to Fig. 6a, 6b, Fig. 7 and 9 (phase margin against 0 deg). This results from the confusion regarding the definition of loop gain (with/without sign inversion) .
Answer from Adam:
Sorry I don’t quite understand this point can you please clarify what you mean. Can you suggest better wording or should it be removed.
In your text, the stability limit is for a loop gain of "-1" (phase: -180deg). However, in the drawings the stability limit is at -360deg (0 deg).
All loop gain simulations include, of course, the sign inversion at the neg. opamp input. This is correct because at low frequencies (including dc) we always require negative feedback. Consequently, the loop gain must be defined as LG(s)=- Aol(s)*beta .
That means: Acl=Aol/(1-LG) and we have instability for LG=+1 (phase: -360 or 0 deg).
With other words: We have to distinguish between (a) the pure product Aol*beta and (b) LG=- Aol(s)*beta. Thus, the contradiction is removed.
Hence, one must speak either about "loop gain" (stability limit at -360 deg) or about the product Aol*beta. But one shouldn´t mix both wordings in one text.
Answer from Adam:
Fc is the cut off frequency the point where the output has fallen 3dB from the original input signal. I understood that -5.7˚ was the point at which it is accepted that attenuation starts, all though I suppose it starts from any signal that’s not d.c. I understood the -84.3˚is the accepted stop band which is 10 times the frequency this adds up to -90 degrees the maximum phase shift a single pole response can give. Is this correct?
To me, this is somewhat confusing (although correct) because this information seems to be totally irrelevant for opamp applications (always with feedback).
Well because of the op-amp input capacitance causing a pole with the source impedance you will only get 180˚ at d.c.
Lvw Said:
No. The 180deg phase shift simply results from the inverting input.
Answer from Adam:
I understand that to achieve exactly 180˚from the start the input would have to be d.c and because the input is a sine wave you will always have a phase shift although at very low frequencies it is very small. Is this correct?
OK - it seems that my first comment was based on a misinterpretation of your sentence. It is correct, that at the opamp output we have -180 deg phase shift for dc input only. However, with rising frequencies the deviation from 180 deg is caused by the frequency properties of the whole amplifier (and not only by the input stage).
A reference buffer that is unstable because of too large a resistance on the input which causes increase loop delay due internal and external capacitances and of course causes a reduction in phase margin.
LVW Said:
No - the input resistance does not degrade stability (By the way: What is the purpose of R8 and R9 ?) . We have instability because of 100% feedback (most critical case) together with an extremely large load capacitor
Answer from Adam:
The input capacitance and large input resistance can cause ringing. Is ringing not classed as a stability issue? R8 and R9 are there to show an example of a circuit that will cause oscillation on start up. The circuit is a poor voltage reference.
As an example, you have selected a circuit which never will be used. Therefore my question: Purpose of R8 nad R9?
More than that, these resistors do not degrade stability. However, the capcitor across the input causes an additional pole for the feedback factor.
Hence, we have additional phase shift for the loop gain function - and the stability is heavily degraded. In addition, the load capacitor deteriorates the situation.
LVW Said: As a consequence, Fig. 17 is meaningless because AC analysis of unstable circuits give no meaningful results, see the plotted gain of 8 dB (for a circuit that should give 20 dB gain).
Answer from Adam:
This shows what happens if someone thinks of filtering the input with a capacitor. It is suppose to show instability. Surely a.c analysis shows whether a circuit is stable or not otherwise why measure phase margin in the first place?
Performing an ac analysis (with an input ac source), requires a stable bias point and linearization around this point (made by the program). However, if a circuit is not stable these conditions are not fulfilled (either the output is clamped at the power rail, or - in case of oscillations - we have two ac sources within the circuit). As a consequence, an ac analysis for unstable circuits in closed-loop conditions are useless - the results are meaningless and false!
If a circuit is unstable, either a TRAN analysis for the closed-loop circuit is to be performed or an ac analysis for the loop gain (demonstration of a negative stability margin) .
Regards
LvW
at first, a general remark to my questions: By asking "why?" I could - in most cases - imagine what you mean (for example: fc) - however, I thought it would be necessary for the reader (newcomer) to know the definition. In general, I think no symbol or abbreviation should be used in any text without a corresponding definition.
Some comments from my side follow:
Answer from Adam:
I was under the impression that when you use negative feedback this reduces the gain uncertainty of the op-amp which in open loop can have quite a high tolerance between the same types of op-amps. Also I thought negative feedback reduced output impedance and increased input impedance. The reduction in output impedance will allow the op-amp to drive higher capacitive loads than when in open loop configuration and the increased input impedance limits the loading on the source driving it. So that’s why I used the word stabilise. Maybe I need to use a different term?
In short: We apply negative feedback to fix/stabilize a DC operating point (like in transistor amplifiers).
At the same time, this is connected with additinal advantages: Increase of input resistance (only non-inverter) , decrease of output resistance, closed-loop gain practically determined by external resistors only, closed-loop bandwidth increase.
However, in electronics each parameter improvement is connected with a degradation of another parameter - in our case: Degradation of dynamic stabilty (stability margin is inversely proportional to the feedback factor). This is demonstrated with the help of loop gain analyses (Nyquist stability criterion).
This is important because if this product ever equals -1 which is -1 <–180 ˚phase shift the circuit could oscillate.
LVW Said:
This is in contrast to Fig. 6a, 6b, Fig. 7 and 9 (phase margin against 0 deg). This results from the confusion regarding the definition of loop gain (with/without sign inversion) .
Answer from Adam:
Sorry I don’t quite understand this point can you please clarify what you mean. Can you suggest better wording or should it be removed.
In your text, the stability limit is for a loop gain of "-1" (phase: -180deg). However, in the drawings the stability limit is at -360deg (0 deg).
All loop gain simulations include, of course, the sign inversion at the neg. opamp input. This is correct because at low frequencies (including dc) we always require negative feedback. Consequently, the loop gain must be defined as LG(s)=- Aol(s)*beta .
That means: Acl=Aol/(1-LG) and we have instability for LG=+1 (phase: -360 or 0 deg).
With other words: We have to distinguish between (a) the pure product Aol*beta and (b) LG=- Aol(s)*beta. Thus, the contradiction is removed.
Hence, one must speak either about "loop gain" (stability limit at -360 deg) or about the product Aol*beta. But one shouldn´t mix both wordings in one text.
Answer from Adam:
Fc is the cut off frequency the point where the output has fallen 3dB from the original input signal. I understood that -5.7˚ was the point at which it is accepted that attenuation starts, all though I suppose it starts from any signal that’s not d.c. I understood the -84.3˚is the accepted stop band which is 10 times the frequency this adds up to -90 degrees the maximum phase shift a single pole response can give. Is this correct?
To me, this is somewhat confusing (although correct) because this information seems to be totally irrelevant for opamp applications (always with feedback).
Well because of the op-amp input capacitance causing a pole with the source impedance you will only get 180˚ at d.c.
Lvw Said:
No. The 180deg phase shift simply results from the inverting input.
Answer from Adam:
I understand that to achieve exactly 180˚from the start the input would have to be d.c and because the input is a sine wave you will always have a phase shift although at very low frequencies it is very small. Is this correct?
OK - it seems that my first comment was based on a misinterpretation of your sentence. It is correct, that at the opamp output we have -180 deg phase shift for dc input only. However, with rising frequencies the deviation from 180 deg is caused by the frequency properties of the whole amplifier (and not only by the input stage).
A reference buffer that is unstable because of too large a resistance on the input which causes increase loop delay due internal and external capacitances and of course causes a reduction in phase margin.
LVW Said:
No - the input resistance does not degrade stability (By the way: What is the purpose of R8 and R9 ?) . We have instability because of 100% feedback (most critical case) together with an extremely large load capacitor
Answer from Adam:
The input capacitance and large input resistance can cause ringing. Is ringing not classed as a stability issue? R8 and R9 are there to show an example of a circuit that will cause oscillation on start up. The circuit is a poor voltage reference.
As an example, you have selected a circuit which never will be used. Therefore my question: Purpose of R8 nad R9?
More than that, these resistors do not degrade stability. However, the capcitor across the input causes an additional pole for the feedback factor.
Hence, we have additional phase shift for the loop gain function - and the stability is heavily degraded. In addition, the load capacitor deteriorates the situation.
LVW Said: As a consequence, Fig. 17 is meaningless because AC analysis of unstable circuits give no meaningful results, see the plotted gain of 8 dB (for a circuit that should give 20 dB gain).
Answer from Adam:
This shows what happens if someone thinks of filtering the input with a capacitor. It is suppose to show instability. Surely a.c analysis shows whether a circuit is stable or not otherwise why measure phase margin in the first place?
Performing an ac analysis (with an input ac source), requires a stable bias point and linearization around this point (made by the program). However, if a circuit is not stable these conditions are not fulfilled (either the output is clamped at the power rail, or - in case of oscillations - we have two ac sources within the circuit). As a consequence, an ac analysis for unstable circuits in closed-loop conditions are useless - the results are meaningless and false!
If a circuit is unstable, either a TRAN analysis for the closed-loop circuit is to be performed or an ac analysis for the loop gain (demonstration of a negative stability margin) .
Regards
LvW
Arouse1973
Adam
Ok I don't know enough about how LT Spice works in that respect, so I'll take your word for it. So basically if transient response shows oscillation then it's pointless doing an a.c analysis on the circuit. But if it is not oscillating we can still look to see how close it might be to oscillating. So would you agree use the scope first then a.c analysis?
*This applies to each simulation program (output clamping or internal oscillation always prevent correct results).
*Yes - if the circuit is stable an AC analysis can reveal a small stability margin (gain peaking) whereas a TRAN analysis will shown overshoot and/or ringing.
Additional remark: Therefore, if it is not clear if a circuit will be stable or not, performing an ac analysis only is rather "dangerous" because it shows something which might be completely wrong. In those cases, it is wise to perform a Tran analysis.
*This applies to each simulation program (output clamping or internal oscillation always prevent correct results).
*Yes - if the circuit is stable an AC analysis can reveal a small stability margin (gain peaking) whereas a TRAN analysis will shown overshoot and/or ringing.
Additional remark: Therefore, if it is not clear if a circuit will be stable or not, performing an ac analysis only is rather "dangerous" because it shows something which might be completely wrong. In those cases, it is wise to perform a Tran analysis.
Last edited:
Arouse1973
Adam
Arouse1973
Adam
hey guys.
I want your input. my next bit is going to be on opamp buffers . Now this simple looking ciruit has some issue if you dont get it right. some opamps that are not unity gain opamps can give issues when used as unity gain buffers. Also when used withh 100% feedback with a short from out to input can cause issues with common input voltage range causing the opamp to shut down or do strange things.
The common fix for this is a resistor across in to out of say 10 K. but this gives issues with offset voltage caused by input bias current. Then you need an input resistor to match the feedback resistor. What do you guys do.
I did message professor Lutz and ask his advice, but he seems to be ignoring me. Oh that is LVW if you didn't know he was a professor at Breman university head of electronics up until 7 years ago. He is probally waiting until I add some more info on opamps before he comments.
Any input most welcome.
Thanks
Adam
I want your input. my next bit is going to be on opamp buffers . Now this simple looking ciruit has some issue if you dont get it right. some opamps that are not unity gain opamps can give issues when used as unity gain buffers. Also when used withh 100% feedback with a short from out to input can cause issues with common input voltage range causing the opamp to shut down or do strange things.
The common fix for this is a resistor across in to out of say 10 K. but this gives issues with offset voltage caused by input bias current. Then you need an input resistor to match the feedback resistor. What do you guys do.
I did message professor Lutz and ask his advice, but he seems to be ignoring me. Oh that is LVW if you didn't know he was a professor at Breman university head of electronics up until 7 years ago. He is probally waiting until I add some more info on opamps before he comments.
Any input most welcome.
Thanks
Adam
Last edited:
Good morning Adam,I did message professor Lutz and ask his advice, but he seems to be ignoring me. Oh that is LVW if you didn't know he is a professor at Breman university head of electronics. He is probally waiting until I add some more info on opamps before he comments.
I am very sorry but until this moment I didn´t know about any message from you. Why should I ignore you?
Is that the picture I have created at your side?
From other forums I know that there is an e-mail if a PM is waitng for me. But I didn´t receive anything.
(By the way and for your information: I am retired since 7 years already).
I will try to answer your question soon.
Adam,
I don´t know if the following will answer your question:
1.) I think, the main reason for using a resistor as feedback element (instead of a short) is input current compensation. In most cases the signal source connected to the non-inv. input has any internal resistance. In this case, there will be a voltage drop caused by the (small) bias current going into the opamp. This voltage drop can pa (partly) compensated by a resistor (app the same value) in the feedback path. This applies also in case of capacitive coupling of the input signal because in this case the dc bias current requires an additional resistor from the non-inv. input to ground.
2.) Regarding stability: I don`t think that the lowpass effect (caused by the internal input capacitance) is the problem for stability. Rather it is the fact that 100 % feedback always is the most critical case - as far as stability is concerned. In this case, the loop gain is at its maximum and the cross-over frequency (0 dB loop gain) is at the maximum possible frequency with a phase shift which also is maximum. Thus, the phase margin is at its lower limit. This causes a step response with overshoot or even with ringing.
I don´t know if the following will answer your question:
1.) I think, the main reason for using a resistor as feedback element (instead of a short) is input current compensation. In most cases the signal source connected to the non-inv. input has any internal resistance. In this case, there will be a voltage drop caused by the (small) bias current going into the opamp. This voltage drop can pa (partly) compensated by a resistor (app the same value) in the feedback path. This applies also in case of capacitive coupling of the input signal because in this case the dc bias current requires an additional resistor from the non-inv. input to ground.
2.) Regarding stability: I don`t think that the lowpass effect (caused by the internal input capacitance) is the problem for stability. Rather it is the fact that 100 % feedback always is the most critical case - as far as stability is concerned. In this case, the loop gain is at its maximum and the cross-over frequency (0 dB loop gain) is at the maximum possible frequency with a phase shift which also is maximum. Thus, the phase margin is at its lower limit. This causes a step response with overshoot or even with ringing.
Arouse1973
Adam
Arouse1973
Adam
Arouse1973
Adam
I read some where it gets a bit more complicated than that.
1) As you have already pointed out the op-amp configured as a buffer is potential the most unstable configuration, unless using a unity gain stable op-amp.
2) When used as a buffer the main thing that can happen on the inputs is with 100% feedback and the lowest output resistance of all the configuration can cause violation of the input common mode voltage range. This can cause the over current protection circuitry to come in drop the output voltage to reduce the current.
3)By placing a resistor in the feedback loop corrects this problem. But causes another two issues. The first is an undesirable offset voltage on the input because of the reaction of the input bias currents and the feedback resistor. The second issue is the new resistor forms an RC network with the input and slows down the loop. When the input starts to increase the output races up to the supply rail as fast as it can. This loop is not yet stabilised because of the delay and so the output overshoots.
4) So the cure I think is this. For the offset voltage we need to match the source input resistance to the feedback resistance to null out the bias currents. The fix for the reduced delay is to by pass the feedback resistor with a small capacitor, this is one of the same fixes for output capacitance loading.
5)Now to use a unity gain buffer as unity gain you need this feedback resistor mentioned above and instead of the cap across the resistor, place a RC network say (2K2 and 39pF) across the inputs. This gives a bit of gain at high frequencies but unity gain at d.c.
What do you think, have I got that right?
1) As you have already pointed out the op-amp configured as a buffer is potential the most unstable configuration, unless using a unity gain stable op-amp.
2) When used as a buffer the main thing that can happen on the inputs is with 100% feedback and the lowest output resistance of all the configuration can cause violation of the input common mode voltage range. This can cause the over current protection circuitry to come in drop the output voltage to reduce the current.
3)By placing a resistor in the feedback loop corrects this problem. But causes another two issues. The first is an undesirable offset voltage on the input because of the reaction of the input bias currents and the feedback resistor. The second issue is the new resistor forms an RC network with the input and slows down the loop. When the input starts to increase the output races up to the supply rail as fast as it can. This loop is not yet stabilised because of the delay and so the output overshoots.
4) So the cure I think is this. For the offset voltage we need to match the source input resistance to the feedback resistance to null out the bias currents. The fix for the reduced delay is to by pass the feedback resistor with a small capacitor, this is one of the same fixes for output capacitance loading.
5)Now to use a unity gain buffer as unity gain you need this feedback resistor mentioned above and instead of the cap across the resistor, place a RC network say (2K2 and 39pF) across the inputs. This gives a bit of gain at high frequencies but unity gain at d.c.
What do you think, have I got that right?
Yes - for my opinion, everything you have stated in points 1) to 4) is correct. However, the main question is: Which of the various effects will dominate for a particular application?
In principle, I agree also to the explanations given by you regarding limitations due to the common mode range. But - is this an important problem for "normal" operation?
I think, this would be a good application for a simulation program. Perhaps I come back to this point tomorrow.
As far as 5.) is concerned, I assume you mean a simple R-C series connection across the input, correct?
In fact, this is a method called "external frequency compensation". If properly designed, such a compensation network will improve the dynamic stability of the buffer (larger phase margin).
It is perhaps surprising, but the gain will not be altered - neither for dc nor for higher frequencies. But - as can be expected - we have to pay a price for this stability improvement:
The bandwidth of the closed loop gain of unity is reduced. This can be verified very easily looking at the loop gain which is reduced for rising frequencies because of the additional R-C path.
LvW
In principle, I agree also to the explanations given by you regarding limitations due to the common mode range. But - is this an important problem for "normal" operation?
I think, this would be a good application for a simulation program. Perhaps I come back to this point tomorrow.
As far as 5.) is concerned, I assume you mean a simple R-C series connection across the input, correct?
In fact, this is a method called "external frequency compensation". If properly designed, such a compensation network will improve the dynamic stability of the buffer (larger phase margin).
It is perhaps surprising, but the gain will not be altered - neither for dc nor for higher frequencies. But - as can be expected - we have to pay a price for this stability improvement:
The bandwidth of the closed loop gain of unity is reduced. This can be verified very easily looking at the loop gain which is reduced for rising frequencies because of the additional R-C path.
LvW
Arouse1973
Adam
Thankyou Lvw.
Hi, here are some simulation results: Overshoot resulting from an input step of 1V.
Opamp LF356 in buffer configuration with various feedback resistors:
* Rf= 0..100 ohms : Vmax=1.1 V
* Rf=1k : Vmax=1.13 V
* Rf=10k : Vmax=1.4 V
* Rf=10k with input compensation (5k in series with 1nF): 1.05 V.
In this case, due to the reduced bandwidth the settling time was drastically increased.
Opamp LF356 in buffer configuration with various feedback resistors:
* Rf= 0..100 ohms : Vmax=1.1 V
* Rf=1k : Vmax=1.13 V
* Rf=10k : Vmax=1.4 V
* Rf=10k with input compensation (5k in series with 1nF): 1.05 V.
In this case, due to the reduced bandwidth the settling time was drastically increased.
Arouse1973
Adam
Hey Lvw
That's great. I'll get the model for that and try this myself. Isn't this fun? And for all of us to work together on these things is great.
Thanks
Adam
That's great. I'll get the model for that and try this myself. Isn't this fun? And for all of us to work together on these things is great.
Thanks
Adam
Arouse1973
Adam
I have added something on buffers now.
Thanks
Adam
Thanks
Adam
Good morning Adam,
I just a short look on the revised post#1 (buffer chapter) and I have the following question:
Why did you choose single supply operation? In this case the circuit can work correctly for positive input voltages only.
Even an input step of 1V is not allowed. For my opinion, such an introductory text should not be based on a specialized circuit with restricted applications.
What do you think?
I just a short look on the revised post#1 (buffer chapter) and I have the following question:
Why did you choose single supply operation? In this case the circuit can work correctly for positive input voltages only.
Even an input step of 1V is not allowed. For my opinion, such an introductory text should not be based on a specialized circuit with restricted applications.
What do you think?
Arouse1973
Adam
Hey Lvw
I thought I would use the most common configuration of buffer seen in most text books and that is single supply operation and I figured most people would use this to buffer voltage higher than the common mode limit? Is this what you mean. Would you like me to mention about the limitations of this configuration. Or add a split supply version.
Cheers
Adam
