Notches in ground planes for multi-power multi-channel board

[Jamie Morken]

Nice circuit, a few parts doing a lot of stuff. The only warning I'd
give Jamie is that he may not want fast edges getting into his
isolated analog stuff, and it would be tricky to slow this one down.
Our thermocouple supply was a classic open-loop forward converter,
dual nfets driving a center-tapped transformer, and we shaped the gate
drives to soften things up. Efficiency didn't matter much here. And we
got a nice clean square wave out of the secondaries, which also
clocked the delta-sigma ADC!

If I disable the PWM to the transformer for a couple cycles during ADC
reading would that get rid of the fast edges and common mode noise
issues?

I fixed the backwards diodes/caps on the positive and negative rails
of the floating bipolar supply:

"http://rocketresearch.nekrom.com/new/isolated bipolar powersupply/isolated bipolar powersupply3.jpg"

cheers,
Jamie

 

[Joerg]

If I disable the PWM to the transformer for a couple cycles during ADC
reading would that get rid of the fast edges and common mode noise
issues?

Yes. Add some big electrolytics in parallel to C22 and C29, the required
capacitance depending on how many cycles of quiet time you need and how
much each rail pulls. You may have to add current limiting to the input
where Q91/Q92 are. Else charging up the big electrolytics at power-up
could take a toll there.

But I wouldn't worry too much about noise if you do a good layout. On
ECG units we never stop the clock.

[...]

 

[John Larkin]

If I disable the PWM to the transformer for a couple cycles during ADC
reading would that get rid of the fast edges and common mode noise
issues?

Absolutely. It's good that you have the resources available to do
that.

I fixed the backwards diodes/caps on the positive and negative rails
of the floating bipolar supply:

"http://rocketresearch.nekrom.com/new/isolated bipolar powersupply/isolated bipolar powersupply3.jpg"

Looks a little complex, especially if you can shut down the switching
during digitizing.

John

 

[Jamie Morken]

Absolutely. It's good that you have the resources available to do
that.

Looks a little complex, especially if you can shut down the switching
during digitizing.

I guess it may make more sense to synchronize the switching with the ADC
sampling (200kHz ADC) since both of these interfaces come from the FPGA.

As long as the common mode/switching noise doesn't last more than a
microsecond or so around each switch point. I wonder if a common mode
choke would exacerbate this problem, may be better to use no common
mode filtering if the switching is synchronized?

cheers,
Jamie

 

[Terry Given]

I guess it may make more sense to synchronize the switching with the ADC
sampling (200kHz ADC) since both of these interfaces come from the FPGA.

As long as the common mode/switching noise doesn't last more than a
microsecond or so around each switch point. I wonder if a common mode
choke would exacerbate this problem, may be better to use no common
mode filtering if the switching is synchronized?

cheers,
Jamie

look up symmetric PWM - rather than a sawtooth, it uses an equilateral
triangle. this is done all the time in 3-phase PWM (AKA Space Vector
Modulation). The peak & trough of the triangle waveform *always*
correspond to the exact center of the high & low pulses. Syncing the ADC
S/H thusly means the sample is always as far as possible from the
switching edges.

and when trying to make, say, sinusoids (its also true for DC) you will
notice that the centre of the pulse is equal to the desired output
current - so sampling like this automagically removes the switching
ripple artefacts.

Cheers
Terry