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need help on clock D flip flops table

Hello
Actually I don't understand what will the output on the falling edge. That's why I made the logic table and try to understand the basic. Is it true for d flip flop
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Is it true for d flip flop
Whatever happens will be determined by whether the flip-flop is triggered by the rising or falling edge of the clock. When the flip-flop is triggered by the clock the 'D' input is latched into the 'Q' output. A 'reset' input, if any, is usually asynchronous & independent of the clock. So is the flip-flop triggered by the rising or falling edge?
 
OK thank you now I understand. Now I am confused on JK flip flop, check the following condition is true or not,
When the both input of jk flip flop is low than output does not change. That means it's store previous value of raising edge
When both input of JK flip flop is high than the output change
 
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