Multiple signals on single Serial TX line

[Klaus Kragelund]

Hi

We are using an Icoupler to transfer TX serial data across a barrier with 115kBaud

I need to transfer a digital signal with low bandwidth across the same barrier

The following link is a initial idea:

www.electronicsdesign.dk/tmp/2Channels_ViaOpto_V0B.pdf

The idea is that the TX data runs through pretty much without being affected to the signal "TX"

On the primary side a circuit can inject a high frequency signal for a short time. On the secondary side the HF signal is caught by the advance of a ripple counter (4017). The clock rate is significantly higher than the TX rate and higher than the reset signal, so when the short time slice with manypulses occurs it will set O3 output high for long enough to charge the "OtherSig" capacitor.

On the surface it behaves well, but I perhaps someone has an better and simpler idea? (I have looked at a microcontroller to decode the signal, but that takes to much current)

I may even be that just a glitch detection circuit could do it, but the ones I have sketched up quickly has too many parts.

Regards

Klaus

 

[mike]

Hi

We are using an Icoupler to transfer TX serial data across a barrier with 115kBaud

I need to transfer a digital signal with low bandwidth across the same barrier

The following link is a initial idea:

www.electronicsdesign.dk/tmp/2Channels_ViaOpto_V0B.pdf

The idea is that the TX data runs through pretty much without being affected to the signal "TX"

On the primary side a circuit can inject a high frequency signal for a short time. On the secondary side the HF signal is caught by the advance of a ripple counter (4017). The clock rate is significantly higher than the TX rate and higher than the reset signal, so when the short time slice with many pulses occurs it will set O3 output high for long enough to charge the "OtherSig" capacitor.

On the surface it behaves well, but I perhaps someone has an better and simpler idea? (I have looked at a microcontroller to decode the signal, but that takes to much current)

I may even be that just a glitch detection circuit could do it, but the ones I have sketched up quickly has too many parts.

Regards

Klaus

Your problem is kinda vague, but if I make some assumptions....
Is there any way you can embed the data in the parity bit and extract
it from the UART parity error flag?

 

[Klaus Kragelund]

Your problem is kinda vague, but if I make some assumptions....

Is there any way you can embed the data in the parity bit and extract

it from the UART parity error flag?

On the primary side (left side), a microcontroller generates the TX signal.It cannot be modified in length or rate, since no intelligent function exists on the secondary side. On the secondary side, the TX signal is brought on to a receiver of unknown type, except that it has an UART to receive thedata

"Combined Data" is the combination of the TX data from the UART and the special signal (with a periodic HF envelope)

The low-rate signal, also generated by the microcontroller, is used to switch on a special circuit on the secondary side. It can be of low rate, updated every 1ms is ok. This signal is free to be modified in a way that supports transfer of the special data

Regards

Klaus

 

[[email protected]]

Your problem is kinda vague, but if I make some assumptions....
Is there any way you can embed the data in the parity bit and extract
it from the UART parity error flag?

The parity bit is a good idea. If all eight bits are being used,
perhaps a stop bit could be added for the same purpose.

 

[Klaus Kragelund]

The parity bit is a good idea. If all eight bits are being used,

perhaps a stop bit could be added for the same purpose.

The TX signal must be transparent to the secondary side with the same widthand timing, so I am afraid this is not possible, although it is a good idea for another case.

Cheers

Klaus

 

[Joerg]

Hi

We are using an Icoupler to transfer TX serial data across a barrier
with 115kBaud

I need to transfer a digital signal with low bandwidth across the
same barrier

The following link is a initial idea:

www.electronicsdesign.dk/tmp/2Channels_ViaOpto_V0B.pdf

The idea is that the TX data runs through pretty much without being
affected to the signal "TX"

On the primary side a circuit can inject a high frequency signal for
a short time. On the secondary side the HF signal is caught by the
advance of a ripple counter (4017). The clock rate is significantly
higher than the TX rate and higher than the reset signal, so when the
short time slice with many pulses occurs it will set O3 output high
for long enough to charge the "OtherSig" capacitor.

On the surface it behaves well, but I perhaps someone has an better
and simpler idea? (I have looked at a microcontroller to decode the
signal, but that takes to much current)

I may even be that just a glitch detection circuit could do it, but
the ones I have sketched up quickly has too many parts.

The classical way would be to do this with a tone decoder, at several
hundred kHz. These are only examples, older models that probably use too
much power and have too many external parts for your case:

http://semicon.njr.co.jp/eng/PDF/NJM2211_E.pdf
http://www.exar.com/Common/Content/Document.ashx?id=170

A second method is to use a PLL chip with lock detect output. It would
lock only if the RF signal is present and stable for a certain time and
the lock output then becomes your OtherSig line. This may be beneficial
if there is EMC concern because you could use an ISM frequency such as
13.56MHz or 27.12MHz.

A third quite unorthodox method would be to use a regenerative circuit
that gets pulled in and out of oscillation by the RF signal. This
oscillation could then either be detected by rectification or by the
difference in current consumption.

 

[Klaus Kragelund]

The classical way would be to do this with a tone decoder, at several

hundred kHz. These are only examples, older models that probably use too

much power and have too many external parts for your case:



http://semicon.njr.co.jp/eng/PDF/NJM2211_E.pdf

http://www.exar.com/Common/Content/Document.ashx?id=170



A second method is to use a PLL chip with lock detect output. It would

lock only if the RF signal is present and stable for a certain time and

the lock output then becomes your OtherSig line. This may be beneficial

if there is EMC concern because you could use an ISM frequency such as

13.56MHz or 27.12MHz.

Nice ideas. The PLL could be done with the 4046, which comes cheap, but not small AFAIR.

Cheers

Klaus

 

[Joerg]

Nice ideas. The PLL could be done with the 4046, which comes cheap, but not small AFAIR.

The 74HC version comes in TSSOP. Do you need higher voltage on the
secondary side?

 

[Tim Williams]

Should be able to cook up a "narrow pulse" detector with some RCs and not
too much complexity (maybe a few schmitt triggers?); alternately, detect
the "low frequency" data with a missing-pulse detector and AND/OR/XOR the
remainder to detect the high frequency stuff.

As far as analog filtering goes, you could make a 25%/75% PWM modulator,
keyed by the 115kb/s data; vary a characteristic of the PWM itself to send
the extra data. Filter and schmitt trigger recovers the 115kb/s data. To
detect the extra data, for example, change it from 25% in the low state to
10% or something. With stop/idle bits, you're guaranteed some minimum
amount of zero bits. Alternately, some delayed-synchronous detection
scheme might yield better noise margin (not that noise is an issue with an
iCoupler and logic level signals).

This is all very NTSC H/Vsync in nature...

Tim

--
Deep Friar: a very philosophical monk.
Website: http://seventransistorlabs.com

Hi

We are using an Icoupler to transfer TX serial data across a barrier with
115kBaud

I need to transfer a digital signal with low bandwidth across the same
barrier

The following link is a initial idea:

www.electronicsdesign.dk/tmp/2Channels_ViaOpto_V0B.pdf

The idea is that the TX data runs through pretty much without being
affected to the signal "TX"

On the primary side a circuit can inject a high frequency signal for a
short time. On the secondary side the HF signal is caught by the advance
of a ripple counter (4017). The clock rate is significantly higher than
the TX rate and higher than the reset signal, so when the short time slice
with many pulses occurs it will set O3 output high for long enough to
charge the "OtherSig" capacitor.

On the surface it behaves well, but I perhaps someone has an better and
simpler idea? (I have looked at a microcontroller to decode the signal,
but that takes to much current)

I may even be that just a glitch detection circuit could do it, but the
ones I have sketched up quickly has too many parts.

Regards

Klaus

 

[Klaus Kragelund]

The 74HC version comes in TSSOP. Do you need higher voltage on the

secondary side?

Max secondary voltage is 3V, so its in the low range.

Right now, I am looking for TinyLogic to see if I can find a counter in that package, but may need to build that using 2 pcs dual Flip flop. (for the original idea with a counter and reset as proposed)

Cheers

Klaus

 

[Klaus Kragelund]

On a sunny day (Mon, 14 Jan 2013 15:56:13 -0800 (PST)) it happened Klaus


<[email protected]>:






It sucks, because you may not get >= 13MHz through a RS232 cable of any significant length.

THe length of the high speed is max 20mm, the low speed (and RC filtered output) of 115k baud has a long run, but thats using a RS485 driver IC

Cheers

Klaus

 

[Joerg]

Max secondary voltage is 3V, so its in the low range.

Right now, I am looking for TinyLogic to see if I can find a counter
in that package, but may need to build that using 2 pcs dual Flip
flop. (for the original idea with a counter and reset as proposed)

You could also try to find a watchdog chip or re-triggerable one-shot
where the time can be set short enough. Should have a Schmitt input.

Then feed its trigger input via a simple bandpass (resonant circuit,
resonator, etc.) so it won't react to the occassional transition that
comes from your 115kbaud traffic but will react if a carrier on the
resonant frequency shows up. SMT-Resonators can be had in very tiny sizes.

 

[[email protected]]

It sucks, because you may not get >= 13MHz through a RS232 cable of any significant length.
Then go wireless!
And take the other data with it.

CAT 3 telephone wiring is capable of carrying 1-24 Mbit/s several
kilometers in DMT modulation (ADSL2+). Within an apartment building,
old telephone wiring will carry much more than that in VDSL format.

 

[[email protected]]

CAT 3 telephone wiring is capable of carrying 1-24 Mbit/s several
kilometers in DMT modulation (ADSL2+). Within an apartment building,
old telephone wiring will carry much more than that in VDSL format.

DSL <> RS232

 

[Syd Rumpo]

Hi

We are using an Icoupler to transfer TX serial data across a barrier with 115kBaud

I need to transfer a digital signal with low bandwidth across the same barrier

The following link is a initial idea:

www.electronicsdesign.dk/tmp/2Channels_ViaOpto_V0B.pdf

The idea is that the TX data runs through pretty much without being affected to the signal "TX"

On the primary side a circuit can inject a high frequency signal for a short time. On the secondary side the HF signal is caught by the advance of a ripple counter (4017). The clock rate is significantly higher than the TX rate and higher than the reset signal, so when the short time slice with many pulses occurs it will set O3 output high for long enough to charge the "OtherSig" capacitor.

On the surface it behaves well, but I perhaps someone has an better and simpler idea? (I have looked at a microcontroller to decode the signal, but that takes to much current)

I may even be that just a glitch detection circuit could do it, but the ones I have sketched up quickly has too many parts.

Regards

Klaus

Take two dual UART PICs or similar. Program one with a 115kbaud UART
receiver which copies to a UART transmitter with a faster baud rate, not
necessarily standard, whatever works with the clock you have. On the
other side of the barrier do the reverse with the other PIC.

Now you have a faster link across the barrier and the world is your
whelk. For example, you could use 9-bit mode on high speed
transmit/receive to select 'normal' serial or your digital signal. Use
digital I/O pin for the digital signal.

Simple code, reliable, cheap.

Cheers

 

[Klaus Kragelund]

On a sunny day (Tue, 15 Jan 2013 04:32:21 -0800 (PST)) it happened Klaus


<[email protected]>:






Then simply use an extra wire for the second channel?

The point of stuffing two signals on the same line is to save an optocoupler across the barrier


Cheers

Klaus

 

[Klaus Kragelund]

You could also try to find a watchdog chip or re-triggerable one-shot

where the time can be set short enough. Should have a Schmitt input.



Then feed its trigger input via a simple bandpass (resonant circuit,

resonator, etc.) so it won't react to the occassional transition that

comes from your 115kbaud traffic but will react if a carrier on the

resonant frequency shows up. SMT-Resonators can be had in very tiny sizes.

Might just do the trick, thanks

Cheers

Klaus

 

[Klaus Kragelund]

Take two dual UART PICs or similar. Program one with a 115kbaud UART

receiver which copies to a UART transmitter with a faster baud rate, not

necessarily standard, whatever works with the clock you have. On the

other side of the barrier do the reverse with the other PIC.



Now you have a faster link across the barrier and the world is your

whelk. For example, you could use 9-bit mode on high speed

transmit/receive to select 'normal' serial or your digital signal. Use

digital I/O pin for the digital signal.



Simple code, reliable, cheap.

That was my first intention, but it takes a new microcontroller and the code for the serial protocol has already been written and this would not be welcome by the sw guys

I could use a small microcontroller to act as the glitch detection, but that would add another microcontroller to be programmed which adds production costs

Cheers

Klaus

 

[Klaus Kragelund]

On a sunny day (Tue, 15 Jan 2013 13:45:42 -0800 (PST)) it happened Klaus


<[email protected]>:






If that solution is more expensive / more complicated than an extra optocoupler, why do it?

Because the optocoupler is a type with extra creepage, and it takes up 50mm2 of realestate. A couple of tiny logic ICs and some 0402s can be done in 10-20mm2

Cheers

Klaus

 

[Joerg]

Because the optocoupler is a type with extra creepage, and it takes
up 50mm2 of realestate. A couple of tiny logic ICs and some 0402s can
be done in 10-20mm2

Check out this type, comes in dual:

http://www.avagotech.com/docs/AV02-1267EN