mosfet circuit - need feedback?

[[email protected]]

Hi,

I'm trying to implement (in spice) some small circuits I've seen in
lectures. I'm hoping that someone can confirm my thinking, with regards
to biasing and feedback.

I've got a basic nmos inverter with pmos load, and I'm generating the
bias for the pmos transistor by mirroring it off a reference, as shown
here:

http://www.flickr.com/photos/tedthornton/313065110/

The W/L ratios of the transistors are: M1,M2=(129/5) and M3=11/1.

At the moment, I'm only interested in biasing the circuit up, so I just
stuck a 1V DC source onto the input of M3. However, the circuit didn't
quite work - the drain current through M2/M3 was only about 85uA and M2
had dropped out of saturation - the voltage at node 4 was 2.93V (so for
M2, Vds=-0.37V, but Vgs-Vt was -0.404V).

After a bit of reading and thinking, I suspected that the voltage at
node 4 was not well defined, so I used a VCVS with gain 1 to feedback
the output node voltage to the input (node 5). This sorted out my
problem - I got 100uA down Id2/id3 and all transistors stayed in
saturation.

So is this the right thing to do? In lectures we considered only the
two transistors M2 and M3 and ignored biasing conditions (ie. just
looked at the AC performance of the circuit). They didn't mention
feedback... is it required?

Cheers,

Ted

 

[Andrew Holme]

Hi,

I'm trying to implement (in spice) some small circuits I've seen in
lectures. I'm hoping that someone can confirm my thinking, with regards
to biasing and feedback.

I've got a basic nmos inverter with pmos load, and I'm generating the
bias for the pmos transistor by mirroring it off a reference, as shown
here:

http://www.flickr.com/photos/tedthornton/313065110/

The W/L ratios of the transistors are: M1,M2=(129/5) and M3=11/1.

At the moment, I'm only interested in biasing the circuit up, so I just
stuck a 1V DC source onto the input of M3. However, the circuit didn't
quite work - the drain current through M2/M3 was only about 85uA and M2
had dropped out of saturation - the voltage at node 4 was 2.93V (so for
M2, Vds=-0.37V, but Vgs-Vt was -0.404V).

After a bit of reading and thinking, I suspected that the voltage at
node 4 was not well defined, so I used a VCVS with gain 1 to feedback
the output node voltage to the input (node 5). This sorted out my
problem - I got 100uA down Id2/id3 and all transistors stayed in
saturation.

So is this the right thing to do? In lectures we considered only the
two transistors M2 and M3 and ignored biasing conditions (ie. just
looked at the AC performance of the circuit). They didn't mention
feedback... is it required?

Cheers,

Ted

Yes, DC feedback is required to control the bias point. Un-buffered CMOS
logic gates can be biased as linear amplifiers by connecting a feedback
resistor from the output to the input. You don't need a VCVS. Just connect
the output to the input.

 

[John Larkin]

Hi,

I'm trying to implement (in spice) some small circuits I've seen in
lectures. I'm hoping that someone can confirm my thinking, with regards
to biasing and feedback.

I've got a basic nmos inverter with pmos load, and I'm generating the
bias for the pmos transistor by mirroring it off a reference, as shown
here:

http://www.flickr.com/photos/tedthornton/313065110/

The W/L ratios of the transistors are: M1,M2=(129/5) and M3=11/1.

At the moment, I'm only interested in biasing the circuit up, so I just
stuck a 1V DC source onto the input of M3. However, the circuit didn't
quite work - the drain current through M2/M3 was only about 85uA and M2
had dropped out of saturation - the voltage at node 4 was 2.93V (so for
M2, Vds=-0.37V, but Vgs-Vt was -0.404V).

After a bit of reading and thinking, I suspected that the voltage at
node 4 was not well defined, so I used a VCVS with gain 1 to feedback
the output node voltage to the input (node 5). This sorted out my
problem - I got 100uA down Id2/id3 and all transistors stayed in
saturation.

So is this the right thing to do? In lectures we considered only the
two transistors M2 and M3 and ignored biasing conditions (ie. just
looked at the AC performance of the circuit). They didn't mention
feedback... is it required?

Cheers,

Ted

The 100 mA is a huge current; is that really 0.1 amps? If the current
mirror works, node 4 will being pulled up very hard, far too hard for
the wimpy n-ch fet to pull it down with just +1 on its gate.

But the Vgs on the topside mirror fets is unreasonable, too, so
something else is wrong. What's the voltage on n1?

Logic gates do not commonly have feedback, unless they're Schmitts.

John

 

[[email protected]]

Hi John,

My apologies, you are right - it should have read 100uA, not
milli-amps. I've made an updated schematic:

http://www.flickr.com/photos/tedthornton/314201349/

Cheers,

Ted

 

[John Larkin]

Hi John,

My apologies, you are right - it should have read 100uA, not
milli-amps. I've made an updated schematic:

http://www.flickr.com/photos/tedthornton/314201349/

Cheers,

Ted

Well, it ought to invert; a real circuit built with real parts sure
would. But +1 is awfully low to turn on the n-fet, depending on the
process of course.

Any idea of the transfer curve of these p and n-channel fets? You
might pull them out of this circuit and simulate each alone, just
plotting Id as a function of Vg, with 3.3 from source to drain. That's
a basic sanity check on the part models. The input logic threshold
will then be the point where the n-ch fet conducts about 100 uA. The
overall circuit should have a huge voltage gain from the n-fet gate to
its drain, once you find the active region.

Plot V4 versus applied V5, over the full V5 range of 0 to +3.3. Should
be an s-curve, pretty steep in the middle.

For extra credit, get some real fets and build the circuit and test
it. Simulation ain't life.

John

 

[[email protected]]

Well, it ought to invert; a real circuit built with real parts sure
would. But +1 is awfully low to turn on the n-fet, depending on the
process of course.

Hi John,

I think there's a misunderstanding here (maybe it's me not
understanding your reply?), I'm not working with logic fets, I'm using
cmos fets for analog design (well, analog design lectures, at least!).
So the +1V DC biases the nmos in saturation, then I can apply my AC
(small-signal) to the input and invert it at the output.

Plot V4 versus applied V5, over the full V5 range of 0 to +3.3. Should
be an s-curve, pretty steep in the middle.

It matches what you describe:

http://www.flickr.com/photos/tedthornton/315215462/

Cheers,

Ted

 

[John Larkin]

Hi John,

I think there's a misunderstanding here (maybe it's me not
understanding your reply?), I'm not working with logic fets, I'm using
cmos fets for analog design (well, analog design lectures, at least!).
So the +1V DC biases the nmos in saturation, then I can apply my AC
(small-signal) to the input and invert it at the output.


It matches what you describe:

http://www.flickr.com/photos/tedthornton/315215462/

Cheers,

Ted

It sure looks like it's working fine. But +1 volt isn't quite enough
to turn on the n-fet decently; you need just a tad more to get it into
the nice steep part of the curve where it has incremental gain.

OK, if you want to use this in its linear region, as an analog amp,
you will need feedback in this stage, or overall feedback in some
bigger external loop, to keep it reliably biased in the good part of
the transfer curve. The threshold voltage isn't predictable enough
that, in real life, you can just jam a dc bias into the fet and expect
it to be in a usable part of the transfer curve.

I mean, you can tweak the bias up to 1.07 or whatever and demonstrate
a large AC gain, but you could never manufacture something like
that... it usually wouldn't work. Hence the need for some sort of
feedback. Or a diffamp or something.

John