F
Francesco
Hi, someone can help me to understand this effect?
I have two inverter in cascade:
inverter inverter
vin---|>----vout1----|>----vout
and I must calculate the propagation time of vout1
The propagation time is defined in my book as the time to decrease from
VDD to VDD/2 or rise from 0 to VDD/2.
I assume the vin rise istantaneusly from 0 to 1 logic, in this situation
the gate-drain capacitor has a terminal that rise from 0 to VDD and the
other terminal decrease from VDD to VDD/2.
For my self it mean that the Miller effect increase the Cgd by a factor
3/2 instead of 2 as my book say!
Where I'm wrong?
Sorry for my english?
Francesco
I have two inverter in cascade:
inverter inverter
vin---|>----vout1----|>----vout
and I must calculate the propagation time of vout1
The propagation time is defined in my book as the time to decrease from
VDD to VDD/2 or rise from 0 to VDD/2.
I assume the vin rise istantaneusly from 0 to 1 logic, in this situation
the gate-drain capacitor has a terminal that rise from 0 to VDD and the
other terminal decrease from VDD to VDD/2.
For my self it mean that the Miller effect increase the Cgd by a factor
3/2 instead of 2 as my book say!
Where I'm wrong?
Sorry for my english?
Francesco