MC10198 monoflop is out of sale

[Robert Baer]

I apprently didn't notice the Monoflop MC10198
went out of sale. Without a successor.
What replacement chip is being taken these days ?
The purpose : make a trigger pulse of few ns a
bit longer.

Rene

Use a delay line and a gate, or just a (slow) gate, or a one
transistor one-shot.

 

[Rene Tschaggelar]

I apprently didn't notice the Monoflop MC10198
went out of sale. Without a successor.
What replacement chip is being taken these days ?
The purpose : make a trigger pulse of few ns a
bit longer.

Rene

 

[Jim Thompson]

I apprently didn't notice the Monoflop MC10198
went out of sale. Without a successor.
What replacement chip is being taken these days ?
The purpose : make a trigger pulse of few ns a
bit longer.

Rene

You might try....

http://www.azmicrotek.com/

and see if they have something that would work.

...Jim Thompson

 

[John Larkin]

I apprently didn't notice the Monoflop MC10198
went out of sale. Without a successor.
What replacement chip is being taken these days ?
The purpose : make a trigger pulse of few ns a
bit longer.

Rene

You can....


|
in---------+--------------------|
| |
| | gate ---------- out
| |
+-----delay----------|
|


which can do all sorts of stuff, depending on the gate and polarities.

The delay can be a trace, an RC, a hunk of coax, another gate, or an
R-L-C.

If you need a real one-shot, you can fire a d-flop and let it reset
itself through a delay.

John




John

 

[Jim Thompson]

You can....


|
in---------+--------------------|
| |
| | gate ---------- out
| |
+-----delay----------|
|


which can do all sorts of stuff, depending on the gate and polarities.

The delay can be a trace, an RC, a hunk of coax, another gate, or an
R-L-C.

If you need a real one-shot, you can fire a d-flop and let it reset
itself through a delay.

John

I've been recently having to do that a lot. Troubles me... I prefer
fully clocked events.

But system "architects" (what a laugh ;-) leave me with undefined
states I have to generate.

I usually...

Set D-Flop with the only "edge" they give me

Delay(s) operate other needed event markers

Final Delay sets R-S Flop

Which sends the RESET

AND a bunch of concluding conditions before RESET clears

Somewhat like the PFD's I've posted here and on my website.

...Jim Thompson

 

[John Larkin]

I've been recently having to do that a lot. Troubles me... I prefer
fully clocked events.

But system "architects" (what a laugh ;-) leave me with undefined
states I have to generate.

I usually...

Set D-Flop with the only "edge" they give me

Delay(s) operate other needed event markers

Final Delay sets R-S Flop

Which sends the RESET

AND a bunch of concluding conditions before RESET clears

Somewhat like the PFD's I've posted here and on my website.

...Jim Thompson

An ecl flop, especially a modern high-gain one like EL or EP, resets
itself nicely. An r-l-c is a good feedback delay, because it gives the
reset a relatively sharp edge and recovers quickly compared to an rc.

A string of gates is a pretty good reset delay inside an ic, which
would be inside an FPGA to us. One trick is to use a string of AND
gates,


in------+--------
| and----------
+-------- and-----------
in---- and---------- out
in-------


which gives a bunch of delay but recovers very quickly.


We sometimes design around FPGA internal cell delays, and we've been
lucky so far.

Sometimes async logic is unavoidable.


John

 

[Fred Bloggs]

I apprently didn't notice the Monoflop MC10198
went out of sale. Without a successor.
What replacement chip is being taken these days ?
The purpose : make a trigger pulse of few ns a
bit longer.

Rene

It is probably gone because there's no need for it. A popular method is
to use the D-FF in the family: apply pulse to 1)CLK input to toggle FF
out of '0' to '1' and 2) pulse thru delay of choice to CLR input.
Another is to use the schmitt differential receiver, hang a cap in
parallel with open emitter termination for fast charge and delayed
discharge, square it up with 2nd schmitt.

 

[Fred Bloggs]

I've been recently having to do that a lot. Troubles me... I prefer
fully clocked events.

But system "architects" (what a laugh ;-) leave me with undefined
states I have to generate.

I usually...

Set D-Flop with the only "edge" they give me

Delay(s) operate other needed event markers

Final Delay sets R-S Flop

Which sends the RESET

AND a bunch of concluding conditions before RESET clears

Somewhat like the PFD's I've posted here and on my website.

...Jim Thompson

How primitive...it's probably relatively unknown today, especially with
regards to the mass produced bit heads who consider themselves 'logic'
designers, but event driven clocking is subsumed within formal
algorithmic state machine theory. Actually it's quite prevalent as most
of the edge triggered logic taken as elemental, like all the FF's, use
this technique in their design.

 

[Jim Thompson]

An ecl flop, especially a modern high-gain one like EL or EP, resets
itself nicely. An r-l-c is a good feedback delay, because it gives the
reset a relatively sharp edge and recovers quickly compared to an rc.

[snip]

I'm immersed in the world of CMOS analog right now... gag me with a
spoon :-(

...Jim Thompson

 

[John Larkin]

[snip]

I'm immersed in the world of CMOS analog right now... gag me with a
spoon :-(

Do you prefer bipolar? I'd expect the processes would be more
repeatable.

John

 

[Jim Thompson]

[snip]

I'm immersed in the world of CMOS analog right now... gag me with a
spoon :-(

Do you prefer bipolar? I'd expect the processes would be more
repeatable.

John

I grew up on bipolar, so I prefer bipolar. It IS more predictable
than CMOS because CMOS has so many defects from the ideal that make
analog design quite tricky.

But BiCMOS provides the best of all worlds. I've designed some nice
WiFi repeaters on BiCMOS.

...Jim Thompson

 

[John Larkin]

[snip]

I'm immersed in the world of CMOS analog right now... gag me with a
spoon :-(

Do you prefer bipolar? I'd expect the processes would be more
repeatable.

John

I grew up on bipolar, so I prefer bipolar. It IS more predictable
than CMOS because CMOS has so many defects from the ideal that make
analog design quite tricky.

But BiCMOS provides the best of all worlds. I've designed some nice
WiFi repeaters on BiCMOS.

...Jim Thompson

Please tell those AZ guys that they could make some money on
comparators.

John

 

[Jim Thompson]

On Thu, 18 Oct 2007 08:15:25 -0700, Jim Thompson
[snip]

I grew up on bipolar, so I prefer bipolar. It IS more predictable
than CMOS because CMOS has so many defects from the ideal that make
analog design quite tricky.

But BiCMOS provides the best of all worlds. I've designed some nice
WiFi repeaters on BiCMOS.

...Jim Thompson

Please tell those AZ guys that they could make some money on
comparators.

John

What kind of specs do you need?

...Jim Thompson

 

[John Larkin]

On Thu, 18 Oct 2007 08:15:25 -0700, Jim Thompson
[snip]

I grew up on bipolar, so I prefer bipolar. It IS more predictable
than CMOS because CMOS has so many defects from the ideal that make
analog design quite tricky.

But BiCMOS provides the best of all worlds. I've designed some nice
WiFi repeaters on BiCMOS.

...Jim Thompson

Please tell those AZ guys that they could make some money on
comparators.

John

What kind of specs do you need?

...Jim Thompson

Single comparator per chip

+-5 supplies; +-3.3 would be nice, too.

Input diff/common mode range +-2.5 volts

Available with ECL or PECL outputs; may as well do LVDS, too.

Prop delay below 1 ns

SO-8 should be available, with the CMP-01/MAX9690 pinout.

John

 

[Tam/WB2TT]

I apprently didn't notice the Monoflop MC10198
went out of sale. Without a successor.
What replacement chip is being taken these days ?
The purpose : make a trigger pulse of few ns a
bit longer.

Rene

You don't need to reinvent the wheel. Use a pair of 2 input ECL NOR gates
with the first stage coupled to the second through a capacitor, and a pullup
at the second stage input.

Tam