LTSpice rounding error?

[Andrew Holme]

Also posted to LTSpice Yahoo Group:

This oscillator is "inter-modulated" by SINE voltage V2, even though the
latter is not connected! Is this due to rounding errors in the solver? Is
there any way to reduce the effect?

TIA


Version 4
SHEET 1 2732 740
WIRE 528 -320 352 -320
WIRE 608 -320 528 -320
WIRE 800 -320 688 -320
WIRE 992 -320 896 -320
WIRE 1168 -320 1072 -320
WIRE 352 -288 352 -320
WIRE 800 -288 736 -288
WIRE 960 -288 896 -288
WIRE 1168 -272 1168 -320
WIRE 528 -256 528 -320
WIRE 304 -224 240 -224
WIRE 240 -176 240 -224
WIRE 736 -160 736 -288
WIRE 960 -160 960 -288
WIRE 1168 -160 1168 -192
WIRE 352 -144 352 -192
WIRE 528 -144 528 -192
WIRE 528 -144 352 -144
WIRE 528 -96 528 -144
WIRE 528 0 528 -32
WIRE 624 0 528 0
WIRE 752 0 704 0
WIRE 1072 0 816 0
WIRE 352 16 352 -144
WIRE 1072 32 1072 0
WIRE 528 48 528 0
WIRE 752 64 752 0
WIRE 352 160 352 96
WIRE 528 160 528 112
WIRE 1072 160 1072 112
FLAG 1168 -160 0
FLAG 352 160 0
FLAG 240 -176 0
FLAG 736 -160 0
FLAG 960 -160 0
FLAG 528 160 0
FLAG 1072 160 0
FLAG 752 64 0
SYMBOL voltage 1168 -288 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 720 -16 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 50
SYMBOL tline 848 -304 M0
SYMATTR InstName T1
SYMATTR Value Td=2n Z0=50
SYMBOL cap 544 -256 M0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL cap 544 -96 M0
SYMATTR InstName C2
SYMATTR Value 33p
SYMBOL cap 544 48 M0
SYMATTR InstName C3
SYMATTR Value 33p
SYMBOL res 368 0 M0
SYMATTR InstName R4
SYMATTR Value 220
SYMBOL voltage 1072 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1e-6 105e6)
SYMBOL njf 304 -288 R0
SYMATTR InstName J1
SYMATTR Value 2N3819
SYMBOL res 704 -336 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 0.1
SYMBOL res 1088 -336 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value 0.1
TEXT 784 -88 Left 0 !.tran 30u

 

[Andrew Holme]

Also posted to LTSpice Yahoo Group:

This oscillator is "inter-modulated" by SINE voltage V2, even though the
latter is not connected! Is this due to rounding errors in the solver?
Is there any way to reduce the effect?

TIA

Helmut over at the Yahoo Group gave me the solution: setting maximum
timestep to 0.1ns

Thanks Helmut!