low voltage buffer IC CMOS design

[jutek]

hello

i'm trying to design a low voltage buffer. i use the circuit as linked here

http://img206.imageshack.us/my.php?image=rail2rail0tq.png

low voltage operation is great. for vdd=1.3V it works very good. the
opamp works in a unity buffer configuration and has 0.1-1V output swing.
with 10uA biasing it has enough driving capabilities for me.

the problem is it doesn't want to work so good for vdd=3.3V. Output
swing is quite low 1V-2.5V.

How to redesign it to have wide output swing also for vdd=3.3V ?

I'd like the out to be about 0.2V - 3.1V

In my design the vdd is variable and changes from 1.3 to 3.3V

Any ideas help or links wanted

regards

 

[Joerg]

Hello Jutek,

i'm trying to design a low voltage buffer. i use the circuit as linked here

http://img206.imageshack.us/my.php?image=rail2rail0tq.png

low voltage operation is great. for vdd=1.3V it works very good. the
opamp works in a unity buffer configuration and has 0.1-1V output swing.
with 10uA biasing it has enough driving capabilities for me.

the problem is it doesn't want to work so good for vdd=3.3V. Output
swing is quite low 1V-2.5V.

Does it absoluetly have to be a CMOS process? How about bipolar? Check
the LM10. That thing runs from just above 1V to 40V supply.

Regards, Joerg

 

[Jim Thompson]

Hello Jutek,



Does it absoluetly have to be a CMOS process? How about bipolar? Check
the LM10. That thing runs from just above 1V to 40V supply.

Regards, Joerg

I think it's homework, so it has to be CMOS ;-)

...Jim Thompson

 

[Joerg]

Hello Jim,

I think it's homework, so it has to be CMOS ;-)

Even then, if it doesn't make sense and there is a much better
alternative to some leaky CMOS design I'd make a strong point about
that. After all, engineers should be trained to have good ideas, spot
bottlenecks, figure out alternatives and not blindly follow some
prescribed recipe.

I did that a few times. The first time was a bit scary because the
assistant prof didn't want to have anything of it. So, I had to make my
case in front of the academic director (2nd in command after the lead
prof) sitting behind a plume of smoke from his pipe. What a relief when
he finally said "Ahm, well, ...., I think you are right". The really
nice thing was that he then asked me whether I'd like to work there.

Regards, Joerg

 

[Jim Thompson]

Hello Jim,


Even then, if it doesn't make sense and there is a much better
alternative to some leaky CMOS design I'd make a strong point about
that.

Your bias is showing ;-) To do rail-rail I/O CMOS is best.

After all, engineers should be trained to have good ideas, spot
bottlenecks, figure out alternatives and not blindly follow some
prescribed recipe.

I did that a few times. The first time was a bit scary because the
assistant prof didn't want to have anything of it. So, I had to make my
case in front of the academic director (2nd in command after the lead
prof) sitting behind a plume of smoke from his pipe. What a relief when
he finally said "Ahm, well, ...., I think you are right". The really
nice thing was that he then asked me whether I'd like to work there.

Regards, Joerg

My famous case was an exam question that had to do with solving the
"trajectory" of an oscillator during start-up.

As originally graded, I was 100% wrong and everyone else had partial
credit.

I went to instructor Jim Melcher (MIT graduate student then, later to
become full professor and then EE Dean) and explained it to him.

He did an "aw-shit", and everyone else was marked wrong and I got full
credit.

I was not popular ;-)

...Jim Thompson

 

[Joerg]

Hello Jim,

Your bias is showing ;-) To do rail-rail I/O CMOS is best.

He didn't say RR. You should be able to get to within his 200mV with
bipolar. Of course, CMOS has a much easier time to do that. But to make
that work from 1.3V to 3.3V for VDD will be a stretch if you want any
kind of performance.

My famous case was an exam question that had to do with solving the
"trajectory" of an oscillator during start-up.

As originally graded, I was 100% wrong and everyone else had partial
credit.

I went to instructor Jim Melcher (MIT graduate student then, later to
become full professor and then EE Dean) and explained it to him.

He did an "aw-shit", and everyone else was marked wrong and I got full
credit.

Had a similar one, telling the academians that it ain't true that RF
transmitters must have a source impedance equal to the antenna or coax
Z. Basically I told them that if that were so they'd hear all the fire
engines rushing to the Deutsche Welle station in the next town right now
because it would be on fire. A few days later I followed that up with
the data sheet of a 'real' AM transmitter, pointing out its efficiency
of over 80%. "Hmmm...., oh drat".

But they didn't re-grade anyone (except me).

Regards, Joerg

 

[jutek]

I think it's homework, so it has to be CMOS ;-)

...Jim Thompson

it's not a homework but it has to be CMOS