Hello, I'm working on a battery-powered alarm project, where the idle current consumption must be as low as possible so that the device can operate for up to a year. Once a sensor trips, I'd like it to turn "on" the rest of the circuit.
Simulation works fine in LTspice using an Enhancement-Mode P-Channel MOSFET. Lets say we have a 7v battery, to the Source of the PMOS and through a 1M pullup to Gate. The Drain connects to the load and ground. 500mA (1.5A peak) will be sunk. The sensor tripping pulls the gate to ground, thus turning on the rest of the circuit. CMOS and TTL logic-level signal voltages are available.
What I'd like to know is, what is the "leakage" current of a PMOS used in this way? For example, the datasheet for a logic-level FDS6575 specifies the "Ioss" or "Zero gate voltage drain current" as a maximum of 1uA. That would be awful for this application (10x more than the sensor currently), so I'd much rather see something in the lines of single nano-amps or less.
If a PMOS isn't the best solution for something like this, I'd appreciate any other ideas.
Thanks!
MJ
Simulation works fine in LTspice using an Enhancement-Mode P-Channel MOSFET. Lets say we have a 7v battery, to the Source of the PMOS and through a 1M pullup to Gate. The Drain connects to the load and ground. 500mA (1.5A peak) will be sunk. The sensor tripping pulls the gate to ground, thus turning on the rest of the circuit. CMOS and TTL logic-level signal voltages are available.
What I'd like to know is, what is the "leakage" current of a PMOS used in this way? For example, the datasheet for a logic-level FDS6575 specifies the "Ioss" or "Zero gate voltage drain current" as a maximum of 1uA. That would be awful for this application (10x more than the sensor currently), so I'd much rather see something in the lines of single nano-amps or less.
If a PMOS isn't the best solution for something like this, I'd appreciate any other ideas.
Thanks!
MJ