Looking for two-input comparator with hysteresis

[Pooh Bear]

Well, they usually do. TI specs +-20 mA for its HC14, with no
footnotes about duration.

Fine if you're using TI but.......

Graham

 

[Fred Bloggs]

If the schmitt is squaring up 60 Hz cycles, how can DC offsets or
"mains variations" affect clock accuracy? If you count each line cycle
exactly once (not zero times, and not twice) where's the error?

The 60 Hz line is sort of the definition of clock time.

John

You are trapped into thinking about steady state. It is the transition
between steady states that causes the error to accumulate over the long
term. The '339 circuit pulls nonlinearly with line amplitude. Therefore
it will accumulate error.

 

[Pooh Bear]

You are trapped into thinking about steady state. It is the transition
between steady states that causes the error to accumulate over the long
term. The '339 circuit pulls nonlinearly with line amplitude. Therefore
it will accumulate error.

Eh ? Come again.

Graham

 

[John Larkin]

Fine if you're using TI but.......

OnSemi specs... +-20 mA. Fairchild is reasonably close, +-20 mA. Now
Philips, on the other hand, specs their abs max esd diode current at
+-20 mA, but the real goofballs are those whacky Italians at ST who
for some reason spec theirs at +-20 mA.

I *wish* these people would get organized.

John

 

[John Larkin]

I still don't feel quite right doing it though. And for just *one resistor*
extra.

Sure, feelings are what really matter.

John

 

[Pooh Bear]

Sure, feelings are what really matter.

Having once experienced device latchup thanks to a certain person's secret
'contribution' to a pcb layout, I prefer to 'play safe'.

Graham

 

[John Larkin]

You are trapped into thinking about steady state. It is the transition
between steady states that causes the error to accumulate over the long
term. The '339 circuit pulls nonlinearly with line amplitude. Therefore
it will accumulate error.

OK, if 5,184,000 sine cycles go into the comparator every day, and
5,184,000 square cycles come out every day, where does the error
accumulate?

John

 

[Pooh Bear]

OK, if 5,184,000 sine cycles go into the comparator every day, and
5,184,000 square cycles come out every day, where does the error
accumulate?

It's sure got me beat !

Graham

 

[John Larkin]

Having once experienced device latchup thanks to a certain person's secret
'contribution' to a pcb layout, I prefer to 'play safe'.

Some parts do still latch, especially mixed-signal stuff. The
LM35/LM45 temperature sensor are horrors, and a lot of ADI and
BurrBrown ADCs and DACs are ghastly as regards latching on overdrive
or improper power-supply sequencing. I've seen systems where a uP
could power-cycle a DAC if it suspected it had latched.

74HC parts are pretty well hardened these days. A few will latch at
extreme esd diode currents, enough to be dangerous in their own right,
and some won't latch at all.

We just did a product where it was really convenient to current-limit
a customer input with Supertex depletion-mode fets (to around 1 mA
max) and dump that into an ADI chopamp, letting the esd diodes clamp
on overvoltage. We tested the parts pretty hard to make sure they
didn't mind, and powered them from shunt regulators to limit supply
current.

Esd diodes are free, so we've just gotta use them!

John

 

[Pooh Bear]

Some parts do still latch, especially mixed-signal stuff. The
LM35/LM45 temperature sensor are horrors, and a lot of ADI and
BurrBrown ADCs and DACs are ghastly as regards latching on overdrive
or improper power-supply sequencing. I've seen systems where a uP
could power-cycle a DAC if it suspected it had latched.

Uhuh. In my case it was an MDAC. And the issue was a brief voltage spike betwen
logic and analogue 0V at power-up. caused by a supply decoupling cap ( that wasn't
on my schematic and got added by the 'helpful guy' ) charging in fact. The
associated trace and current created enough volts across it's resistance on
power-on to latch the chip. Luckily they didn't break but just got very warm.

74HC parts are pretty well hardened these days. A few will latch at
extreme esd diode currents, enough to be dangerous in their own right,
and some won't latch at all.

I take your point.

We just did a product where it was really convenient to current-limit
a customer input with Supertex depletion-mode fets (to around 1 mA
max) and dump that into an ADI chopamp, letting the esd diodes clamp
on overvoltage. We tested the parts pretty hard to make sure they
didn't mind, and powered them from shunt regulators to limit supply
current.

How long did the testing take ( cost ) vs using other methods to clamp the volts ?

Esd diodes are free, so we've just gotta use them!

Makes me cringe though.

Graham

 

[Robert Latest]

On Wed, 24 May 2006 22:12:24 +0000,

Thanks for the very useful advice. I'm looking for something simple
which just works reliably, and this seems to fit the bill. If I've done
my calculations right a potential divider consisting of a 100k ohm
resistor and 22 nF capacitor gives a maximum voltage of around 10 V
between the Schmitt trigger input and logic ground (for a 50 Hz signal).

Don't think potential here. You might even omit the capacitor. Your
circuit is relying on the input protection diodes of the schmitt (check
your data sheet) to limit the input voltage. The cap is just there to
filter out multiple triggering by runt pulses on the AC line.

robert

 

[Robert Latest]

On Fri, 26 May 2006 00:26:55 +0100,

Actually, yout 12V ac winding will produce about 17V pk-pk so a PD of just
greater than 3:1 should be used.

Not necessary, as I already pointed out. Let the voltage be clamped by
the IP diodes. The resistor is just a current limiter, with some
filtering action thrown in by the cap.

robert

 

[Robert Latest]

On Wed, 24 May 2006 23:12:50 -0400,

Yes. He was suggesting a schmitt trigger or comparitor doing the
filtering. In that case the isolator is *not* an additional
component. He's building *ONE*. Yes, I am worried about his
safety over the cost of an optical isolator. (yikes! you really
can't be that dumb)

I just can't see the point of using an optical insulator fore *safety*
reasons in a circuit which has both sides of the insulator connected
galvanically anyway. If the transformer insulation fails, the whole
circuit is live. On both sides of the isolator.

robert

 

[Fred Bloggs]

OK, if 5,184,000 sine cycles go into the comparator every day, and
5,184,000 square cycles come out every day, where does the error
accumulate?

John

When the mains amplitude climbs to a new magnitude, the '339 triggers
increasingly early during the cycles comprising the transition- and
"early" is relative to the trigger period prior to the amplitude change.
These trigger period transitions will be different from those due to a
mains amplitude decrease, because of the waveform input to the '339.
Mean trigger cycle perturbations do not zero- they accumulate- the
circuit is weighting the perturbations due to mains amplitude decrease
by more than the increase. And even if the weighting is equalized, there
is no reason for the mains fluctuation to zero, it will be a function of
the energy profile of the grid.

 

[Spehro Pefhany]

When the mains amplitude climbs to a new magnitude, the '339 triggers
increasingly early during the cycles comprising the transition- and
"early" is relative to the trigger period prior to the amplitude change.
These trigger period transitions will be different from those due to a
mains amplitude decrease, because of the waveform input to the '339.
Mean trigger cycle perturbations do not zero- they accumulate- the
circuit is weighting the perturbations due to mains amplitude decrease
by more than the increase. And even if the weighting is equalized, there
is no reason for the mains fluctuation to zero, it will be a function of
the energy profile of the grid.

Who are you and what have you done with 'Fred Bloggs'?


Best regards,
Spehro Pefhany

 

[John Larkin]

How long did the testing take ( cost ) vs using other methods to clamp the volts ?

Just an hour or two. Explicit clamping would take room (the circuit is
very tight), add more supplies, complicate headroom and linearity
issues, and add leakage in a circuit where we begrudge every picoamp.

Makes me cringe though.

A Real Man does what he Has To Do.

John

 

[John Larkin]

Who are you and what have you done with 'Fred Bloggs'?

Thanks, Speff. You saved me a lot of typing.

John

 

[Jim Thompson]

John Larkin wrote: [snip]

The 60 Hz line is sort of the definition of clock time.

John

You are trapped into thinking about steady state. It is the transition
between steady states that causes the error to accumulate over the long
term. The '339 circuit pulls nonlinearly with line amplitude. Therefore
it will accumulate error.

What BS!

...Jim Thompson

 

[Keith]

Nah ! All digital circuits are really analogue if you look properly.

Nah, if you look closer they're all digital (see: Plank). ;-)

 

[Keith]

Power maybe ? I can't see anyone designing a battery clock that has to be
connected to the mains to get its reference frequency !

It's fairly common, actually. The mains frequency is far better
than you're likely to find at a reasonable cost otherwise.