Is there anything wrong with running a trace between the pads of another component?

[M. Noone]

Hi - I was wondering, when can you, and when can you not, run traces
between the pads of other components? For example - is there anything
wrong with running relatively fast (~5Mhz) digital lines between the
pads of a 0603 .1uf decoupling capacitor? What about running traces
between the pads of chips? (though this hardly ever is possible with
surface mount chips - but with SOICs I think it sometimes is). I've
always avoided doing this - but now I'm starting to realize that it
might not be something I really need to be worrying about.

Thanks!

-Mike

PS sorry if this gets posted twice - having Internet problems + google
groups problems

 

[Boris Mohar]

Hi - I was wondering, when can you, and when can you not, run traces
between the pads of other components? For example - is there anything
wrong with running relatively fast (~5Mhz) digital lines between the
pads of a 0603 .1uf decoupling capacitor? What about running traces
between the pads of chips? (though this hardly ever is possible with
surface mount chips - but with SOICs I think it sometimes is). I've
always avoided doing this - but now I'm starting to realize that it
might not be something I really need to be worrying about.

Thanks!

-Mike

PS sorry if this gets posted twice - having Internet problems + google
groups problems

As long as it passes the DRC there is nothing wrong with that. I use 5thou
spacing with 5thou copper tracks Sometimes I go lower than that.



Regards,

Boris Mohar

Got Knock? - see:
Viatrack Printed Circuit Designs (among other things) http://www.viatrack.ca

void _-void-_ in the obvious place

 

[Terry Given]

Hi - I was wondering, when can you, and when can you not, run traces
between the pads of other components? For example - is there anything
wrong with running relatively fast (~5Mhz) digital lines between the
pads of a 0603 .1uf decoupling capacitor? What about running traces
between the pads of chips? (though this hardly ever is possible with
surface mount chips - but with SOICs I think it sometimes is). I've
always avoided doing this - but now I'm starting to realize that it
might not be something I really need to be worrying about.

Thanks!

-Mike

I do it all the time. I modified my IPC-SM-782 0603 footprint very
slightly, it now allows an 8/8/8 gap/track/gap thru the pads of an 0603.

what you really care about is capacitive and inductive crosstalk. the
capacitive side of things is easy to calculate. high dV/dt nodes (eg
74AHC logic, ECL) can cause problems with tiny coupling capacitances, if
they go into a high-Z node. I once had an issue with 60fF (0.06nF) from
a digital output to the summing node of an opamp, where it caused 200mV
spikes on my +/-10V analogue output.

so providing you understand what your signal does and where it goes, all
is fine.

OTOH if you "just do it" without paying attention to what happens
electrically, Murphy will get you

I'm working on a 10-layer 1-Oz/2-Oz PCB at the moment, 160mm x 213mm,
completely covered in smt components, about 2500 of them. so many parts
on one side there is very little room for vias, which are tiny (12mil,
and 35,000 of them)

Cheers
Terry

 

[Winfield Hill]

Terry Given wrote...

what you really care about is capacitive and inductive crosstalk. the
capacitive side of things is easy to calculate. high dV/dt nodes (eg
74AHC logic, ECL) can cause problems with tiny coupling capacitances, if
they go into a high-Z node. I once had an issue with 60fF (0.06nF) from
a digital output to the summing node of an opamp, where it caused 200mV
spikes on my +/-10V analogue output.

A good rule is to keep everything away from the wires making
up the summing junction node. And keep those traces short.

 

[Terry Given]

Terry Given wrote...

0.06pF oops

A good rule is to keep everything away from the wires making
up the summing junction node. And keep those traces short.

indeed.

In this case it was a very short length of inner trace, 8mil from the
-ve input trace. Of course it was a poor layout that allowed that to
happen in the first place, but I was surprised at how small the
calculated capacitance was when I checked the PCB layout. So I measured
the spike carefully, along with dV/dt on the offending signal, and sure
enough

I = Ccoupling*dV/dt

injected into the high impedance summing node caused the observed output
spikes. I tested the theory in spice, and then managed to isolate the
offending trace by drilling out a couple of vias, and manually
re-routing the trace. Voila, no spikes. routing the wire past the opamp
input made the spikes come back.

it was a pretty good introduction to how circuit layout affects performance.

Cheers
Terry

 

[Mac]

Hi - I was wondering, when can you, and when can you not, run traces
between the pads of other components? For example - is there anything
wrong with running relatively fast (~5Mhz) digital lines between the
pads of a 0603 .1uf decoupling capacitor? What about running traces
between the pads of chips? (though this hardly ever is possible with
surface mount chips - but with SOICs I think it sometimes is). I've
always avoided doing this - but now I'm starting to realize that it
might not be something I really need to be worrying about.

Thanks!

-Mike

PS sorry if this gets posted twice - having Internet problems + google
groups problems

It really depends on the signal. For clock traces I think I would try to
keep 15 or 20 mil spacing, which would probably preclude snaking through
an 0603, but for other signals I would definitely consider it.

You always want to make sure that your board fab people can handle
whatever spacing you use, of course.

--Mac

 

[Roy L. Fuchs]

I'm working on a 10-layer 1-Oz/2-Oz PCB at the moment, 160mm x 213mm,
completely covered in smt components, about 2500 of them. so many parts
on one side there is very little room for vias, which are tiny (12mil,
and 35,000 of them)

Deep, digital design. Sounds pretty dense <sic>.

 

[Roy L. Fuchs]

0.06pF oops


indeed.

In this case it was a very short length of inner trace, 8mil from the
-ve input trace. Of course it was a poor layout that allowed that to
happen in the first place, but I was surprised at how small the
calculated capacitance was when I checked the PCB layout. So I measured
the spike carefully, along with dV/dt on the offending signal, and sure
enough

I = Ccoupling*dV/dt

injected into the high impedance summing node caused the observed output
spikes. I tested the theory in spice, and then managed to isolate the
offending trace by drilling out a couple of vias, and manually
re-routing the trace. Voila, no spikes. routing the wire past the opamp
input made the spikes come back.

it was a pretty good introduction to how circuit layout affects performance.

Cheers
Terry

This whole thread is pretty cool. It should go down as a required
read... somewhere. ;-]

 

[John Larkin]

I do it all the time. I modified my IPC-SM-782 0603 footprint very
slightly, it now allows an 8/8/8 gap/track/gap thru the pads of an 0603.

what you really care about is capacitive and inductive crosstalk. the
capacitive side of things is easy to calculate. high dV/dt nodes (eg
74AHC logic, ECL) can cause problems with tiny coupling capacitances, if
they go into a high-Z node. I once had an issue with 60fF (0.06nF) from
a digital output to the summing node of an opamp, where it caused 200mV
spikes on my +/-10V analogue output.

so providing you understand what your signal does and where it goes, all
is fine.

OTOH if you "just do it" without paying attention to what happens
electrically, Murphy will get you

I'm working on a 10-layer 1-Oz/2-Oz PCB at the moment, 160mm x 213mm,
completely covered in smt components, about 2500 of them. so many parts
on one side there is very little room for vias, which are tiny (12mil,
and 35,000 of them)

Good grief, what needs that many parts? And 14 vias per part is an
interesting metric.

We recently did a 6-layer VME board with about 1050 parts, and it was
pretty well paved over, with a mere 2300 15-mil vias.

If you show us a picture of your board, I'll show a pic of mine.

John

 

[Harry Dellamano]

Good grief, what needs that many parts? And 14 vias per part is an
interesting metric.

We recently did a 6-layer VME board with about 1050 parts, and it was
pretty well paved over, with a mere 2300 15-mil vias.

If you show us a picture of your board, I'll show a pic of mine.

John

14 vias per part, I love it, must be thermal vias for heat flow. Each
thermal via is about 50C/W so 50/14 = 3.6C/watt which is a nice thermal
resistance. Then you put thermal spreaders to thermal layers, (4 oz cu) and
then to the heat sink and conductive cooling. Been there, done that!
If vias for high current, then about 3Amps per via and you are playing with
14*3 = 42A. BTDT.
Show us your creation, may hang on bedroom wall.
Cheers,
Harry

 

[Terry Given]

0.06pF oops



indeed.

In this case it was a very short length of inner trace, 8mil from the
-ve input trace. Of course it was a poor layout that allowed that to
happen in the first place, but I was surprised at how small the
calculated capacitance was when I checked the PCB layout. So I measured
the spike carefully, along with dV/dt on the offending signal, and sure
enough

I = Ccoupling*dV/dt

injected into the high impedance summing node caused the observed output
spikes. I tested the theory in spice, and then managed to isolate the
offending trace by drilling out a couple of vias, and manually
re-routing the trace. Voila, no spikes. routing the wire past the opamp
input made the spikes come back.

it was a pretty good introduction to how circuit layout affects performance.

Cheers
Terry

This whole thread is pretty cool. It should go down as a required
read... somewhere. ;-]

you'd have liked the train of events with that particular measurement
then. it went something like this:

- aha, evil spikes. that must be coupling I reckon

- aha, its exactly synchronous with the PWM, its either feedthru or coupling

- aha, the passively filtered PWM node (before the opamp filter) doesnt
have spikes, it must be coupling into the opamp from the raw PWM, lets
look at the artwork

- aha, the PWM trace runs right beside the summing input trace on an
inner layer. lets calculate C

- WTF? 60fF ?! ya bollocks

- ok, measure spike amplitude (200mV) and dV/dt(5V/5ns) of PWM signal

- then calculate Ic = 60fF*5V/5ns = 60uA

- then divide Vspike by Ic to get 3~4kOhms

- look at impedance of summing node. guess what....

It was also about then that I read "controlling conducted emissions by
design" and "controlling radiated emissions by design". Both of which
thrashed to death one main point - its the circuit you physically build,
rather than the one you drew up in a schematic editor, that really
counts. just like RF really.

I'd say LTs AN47 is required reading (thanx Jim Williams)

Cheers
Terry

 

[Terry Given]

Good grief, what needs that many parts? And 14 vias per part is an
interesting metric.

If I said, they'd kill me

It is an interesting metric, and one which I intend to reduce. I'd be
happy with 8 per part

We recently did a 6-layer VME board with about 1050 parts, and it was
pretty well paved over, with a mere 2300 15-mil vias.

If you show us a picture of your board, I'll show a pic of mine.

John

I'd love to, John, but alas I cant.

If it makes you feel better, the existing layer ordering is set up to
maximise inductive and resistive crosstalk. I can get an order of
magnitude reduction by swapping 2 layers.

it also appears to have been autorouted, and they havent taken advantage
of the many available symmetries/patterns to simplify layout. it took a
guy 5 weeks to layout, and that they achieved this level of density is
amazing.

Cheers
Terry

 

[Terry Given]

14 vias per part, I love it, must be thermal vias for heat flow. Each
thermal via is about 50C/W so 50/14 = 3.6C/watt which is a nice thermal

where do you get this figure? what size "thermal" via?

resistance. Then you put thermal spreaders to thermal layers, (4 oz cu) and
then to the heat sink and conductive cooling. Been there, done that!

did that but with a 20mm air gap to the heatsink. it was only a 55W
2.8V/3.9V smps, but all FETs were SOIC8, and the heatsink was a 150mm x
150mm Al plate in the plastic enclosure, about 20mm from the pcb

If vias for high current, then about 3Amps per via and you are playing with
14*3 = 42A. BTDT.

again, interesting numbers, where do they originate?

Show us your creation, may hang on bedroom wall.

not my creation, my job to improve. alas cant show it

Cheers,
Harry

Cheers
Terry

 

[Roy L. Fuchs]

maximise

Wouldn't the desire to be MINIMIZE?

 

[Harry Dellamano]

Harry Dellamano wrote:

where do you get this figure? what size "thermal" via?


did that but with a 20mm air gap to the heatsink. it was only a 55W
2.8V/3.9V smps, but all FETs were SOIC8, and the heatsink was a 150mm x
150mm Al plate in the plastic enclosure, about 20mm from the pcb


again, interesting numbers, where do they originate?


not my creation, my job to improve. alas cant show it


Cheers
Terry

Hi Terry,
I live in a simple world of basic algebra to solve most problems. If
algebra will not work, I then revert to SPICE. So thermal resistance of
copper is:
Rt= C/W = 0.10*Length/Area (inches). Change the 0.10 for materials other
than copper.
So for a thermal via in a 0.062" PCB of 0.028" diameter is:
Rt= 0.10*0.062/(3.14*0.028*0.0014) = 50C/W.
The optimum thermal via diameter to minimize thermal resistance in a fixed
area is left to the student. It also depends if solder will wick into the
via. I have done 1200 thermal vias under a standard power module (4"x2")
dissipating 40 watts and have less than 4C drop in a 0.092" PCB.
Cheers,
Harry

 

[Terry Given]

Hi Terry,
I live in a simple world of basic algebra to solve most problems. If
algebra will not work, I then revert to SPICE. So thermal resistance of
copper is:
Rt= C/W = 0.10*Length/Area (inches). Change the 0.10 for materials other
than copper.
So for a thermal via in a 0.062" PCB of 0.028" diameter is:
Rt= 0.10*0.062/(3.14*0.028*0.0014) = 50C/W.
The optimum thermal via diameter to minimize thermal resistance in a fixed
area is left to the student. It also depends if solder will wick into the
via. I have done 1200 thermal vias under a standard power module (4"x2")
dissipating 40 watts and have less than 4C drop in a 0.092" PCB.
Cheers,
Harry

Hi Harry,

lovely, thanks. I figured thats what you did, but I'm running around
like a blue-arsed fly at the moment, and it was easier to just ask.

Ya gotta love electronics

Cheers
Terry

 

[Terry Given]

Wouldn't the desire to be MINIMIZE?

well yes, you'd think so. Alas, thats not what happened. Send a digital
boy to do an analogue mans job....

Besides, I think you mean minimise

Cheers
Terry

 

[John Larkin]

Hi Terry,
I live in a simple world of basic algebra to solve most problems. If
algebra will not work, I then revert to SPICE. So thermal resistance of
copper is:
Rt= C/W = 0.10*Length/Area (inches). Change the 0.10 for materials other
than copper.
So for a thermal via in a 0.062" PCB of 0.028" diameter is:
Rt= 0.10*0.062/(3.14*0.028*0.0014) = 50C/W.
The optimum thermal via diameter to minimize thermal resistance in a fixed
area is left to the student. It also depends if solder will wick into the
via. I have done 1200 thermal vias under a standard power module (4"x2")
dissipating 40 watts and have less than 4C drop in a 0.092" PCB.
Cheers,
Harry

Our r.o.t. is 70 K/w and 500 uohms per square of 1 oz copper. So a
fat via, a 20 mil drill, in a 62 mil board has about a square of
copper in the bore so is roughly 70 k/w and 500 uohms side-to-side. Of
course, the plating won't really be 1 oz, and the via may be filled
with solder (not often these days, what with surfmount reflow.)

You rarely get 1 oz copper these days, even when you spec it.

Given a certain available area to transfer heat from side to side,
what's better, a few big vias or a lot of little ones?

Interestingly, one ohm of copper, or most other common metals, has a
thermal resistance of around 150,000 k/w.

John

 

[Fred Bartoli]

Our r.o.t. is 70 K/w and 500 uohms per square of 1 oz copper. So a
fat via, a 20 mil drill, in a 62 mil board has about a square of
copper in the bore so is roughly 70 k/w and 500 uohms side-to-side. Of
course, the plating won't really be 1 oz, and the via may be filled
with solder (not often these days, what with surfmount reflow.)

You rarely get 1 oz copper these days, even when you spec it.

Given a certain available area to transfer heat from side to side,
what's better, a few big vias or a lot of little ones?

If you pack N vias of d diameter in a line such that they touch each other
the N vias are equivalent to a big D=N.d via
So the thermal resistance decrease as 1/N for a compact set of vias inside a
square (N.d)^2.
Of course the gain will not be this big, but the advantage is still way in
favor to N small vias.

Interestingly, one ohm of copper, or most other common metals, has a
thermal resistance of around 150,000 k/w.

Now that seems a pretty nice and useless figure to throw up in air during
some meeting.
Just look at those jumping on their pencil to take note and you'll know who
to not work with.

 

[Harry Dellamano]

Our r.o.t. is 70 K/w and 500 uohms per square of 1 oz copper. So a
fat via, a 20 mil drill, in a 62 mil board has about a square of
copper in the bore so is roughly 70 k/w and 500 uohms side-to-side. Of
course, the plating won't really be 1 oz, and the via may be filled
with solder (not often these days, what with surfmount reflow.)

You rarely get 1 oz copper these days, even when you spec it.

Given a certain available area to transfer heat from side to side,
what's better, a few big vias or a lot of little ones?

Interestingly, one ohm of copper, or most other common metals, has a
thermal resistance of around 150,000 k/w.

John

Your 70K/w for a 20 mil dia hole is the same as my 50C for a 28 mil hole.
500uR per 1 oz square cu works for me too.
Given a fixed heat transfer area and no solder fill, a lot of little vias
are better than one big air hole.
Let's check your 150K k/w with a 20" x 0.010" 1 ohm cu trace:
Rt= 0.1*20/(.010*.0014) = 143K.. not too bad!
Do you use/agree with any of the trace width calculators or even IPC(2222)
that are based on convection cooling? They work for me when the trace is
1.50" long, shorter traces can be thinner, longer traces must be fatter.
Most PCB have internal planes that spread heat and thermal conduction in
traces greatly out performs thermal convection. I strive for <12mV drop in
all traces. This will keep temp rise in all traces to <5C due to conductive
cooling at the trace end points.
Cheers,
Harry