For the benefit of anyone else reading this thread, here are the three pages of the data sheet:
I haven't seen this type of device before, so I'll have to make some guesses and assumptions.
It looks like each element is a P-channel JFET, and a diode. A P-channel JFET is turned OFF by applying a positive voltage to its gate (this voltage must be positive with respect to both the source and drain, which are interchangeable). When the gate voltage is roughly equal to the drain and source voltages, it will conduct. This fits with the description in the data sheet that says "A logic "0" turns the channel ON and a logic "1" turns the channel OFF".
As for what it does, and what the diode is there for, have a look at how it's used in your circuit.
The circuit formed by U13 is an integrator, using C35, which provides the negative feedback path around U13 so that U13 can keep point C at the same voltage as point D. Point D is at 0V, so point C will also be at 0V unless the integrator is saturated.
The input to the integrator is a current applied at point C, which comes from three sources: point A via R113, from another part of the circuit via R110, and when the JFET is ON, from point A via R85, which is ten times lower than R113. So the JFET switch is used to increase the scale of the voltage at point A.
The circuit also has a feedback loop marked F. If you describe what the circuit does, I may be able to explain how it works.
As I said before, the JFET is controlled by its gate voltage at point G, which the JFET takes relative to its source and drain. A JFET is symmetrical and its source and drain are interchangeable. To turn a P-channel JFET OFF, the gate must be made several volts positive relative to both the source and the drain. Therefore if the JFET is to be controlled properly, both the source and drain must be prevented from having a significant positive voltage on them. A positive voltage on either the source or drain would reduce the reverse bias caused by the positive voltage at the gate, and the JFET would start to conduct when it shouldn't.
So both the source and drain must be kept from going significantly positive. The right hand terminal, connected to point C, is always at 0V because of the action of U13. But the left hand terminal, point B, will be brought positive by R85 if point A goes positive. This is the reason for the diode, whose cathode is connected to 0V. It prevents point B from going significantly positive, which would cause the JFET to see less reverse bias on the gate and would make it start to conduct.
The diode doesn't affect the operation of the circuit, because point A is a low-impedance point at the output of U10. All it will do is clip the voltage at point B to about +0.6V. Since R85 is such a high value, this will have no effect on the rest of the circuit.
