J
Jim Thompson
Conserning use of comparators and SR latchs to make a hysteresis
comparator..
I'm keeping an eye on that SR latch idea..
The SR latch has that illegal input state (race condition).
My spec is 100mV of hysteresis and this circuit is part of a
smps controller..
Could be like finding a quiet spot in a noisey dance club
I suspect as hysteresis approachs 0 there's more probability
that the SR latch gets simultaneous S and R signals due to noise
presented to the comparators. Just getting scared by this quirk,
but I won't rule it out yet..
I had to review my latch operation and found:
http://www.allaboutcircuits.com/vol_4/chpt_10/4.html
Which describes the D latch without illegal states.
For choice of latch in the circuit...
Perhaps SR is good for wide hystersis and clean signals and D
latch for small hysteresis and dirty signals??
D
Except that the circuit at the above URL is NOT a "D-latch" in the
conventional sense of the word... a "D-latch" is edge-triggered, and
the circuit at the URL is "re-settable" as long as "E" is high and
thus is called a "transparent latch".
...Jim Thompson