Hysteresis Comparator Methods

[D from BC]

I've seen various hysteresis circuits in app notes such as:
http://pdfserv.maxim-ic.com/en/an/AN3616.pdf

I'm not familiar with this method:

The signal is applied to 2 comparators (no feedback) which are
connected to a D type latch.
(Longer discription by request.)

One benefit I see is that both comparators can get clean stable
references.

Anybody familiar with the drawbacks of the 2 comparator D latch
combo to make a hysteretic comparator?
Is this a vastly superior circuit compared to what's seen in app
notes?
D

 

[John Larkin]

I've seen various hysteresis circuits in app notes such as:
http://pdfserv.maxim-ic.com/en/an/AN3616.pdf

This appnote is seriously bogus, in that it totally ignores the
time-domain aspect of the positive feedback. Figure 7 is especially
pernicious. Unless very carefully thought out, including consideration
of the slew rate and noise characteristics of the input signal, the
conventional hysteresis circuit can propagate glitches contrary to its
claimed bahavior.

This appnote is a great example of simplistic, intuitive analysis
that's just wrong.

I'm not familiar with this method:

The signal is applied to 2 comparators (no feedback) which are
connected to a D type latch.
(Longer discription by request.)

One benefit I see is that both comparators can get clean stable
references.

Anybody familiar with the drawbacks of the 2 comparator D latch
combo to make a hysteretic comparator?
Is this a vastly superior circuit compared to what's seen in app
notes?
D

This can be a lot better, because there's no delay coming back around
into a positive-feedback node, and because the comparator prop delays
are effectively pipelined... everything flows left-to-right. The
comparators still have to be well behaved and well characterized,
specifically to have fairly symmetric rising and falling edge prop
delays. But this configuration has fewer screwup modes.

The other nice thing here is that the two comparator references can be
programmed with DACs, allowing thresholds and hysteresis to be under
software control. I use this configuration in my tachometer
conditioning modules, and it's very flexible.

John

 

[Jim Thompson]

This appnote is seriously bogus, in that it totally ignores the
time-domain aspect of the positive feedback. Figure 7 is especially
pernicious. Unless very carefully thought out, including consideration
of the slew rate and noise characteristics of the input signal, the
conventional hysteresis circuit can propagate glitches contrary to its
claimed bahavior.

This appnote is a great example of simplistic, intuitive analysis
that's just wrong.


This can be a lot better, because there's no delay coming back around
into a positive-feedback node, and because the comparator prop delays
are effectively pipelined... everything flows left-to-right. The
comparators still have to be well behaved and well characterized,
specifically to have fairly symmetric rising and falling edge prop
delays. But this configuration has fewer screwup modes.

The other nice thing here is that the two comparator references can be
programmed with DACs, allowing thresholds and hysteresis to be under
software control. I use this configuration in my tachometer
conditioning modules, and it's very flexible.

John

Then there's the optimum method I devised in my MC1650/51 design in
the mid '60's ;-)

...Jim Thompson

 

[John Larkin]

Then there's the optimum method I devised in my MC1650/51 design in
the mid '60's ;-)

...Jim Thompson

Hysteresis internal to ICs can be a lot better, because you can
localize the positive feedback into a very tight, single-pole loop.
The HC14 type schmitts are apparently immune from teasing, too.

Opamps often make better comparators than comparators, because they
have one dominant pole and don't store as much information as the
usual fast-multistage comparator topology.

It's funny that the common comparator-plus-hysteresis circuit is
almost universally taught as being a clever thing, taught by people
who don't understand it.

John

 

[Genome]

Hysteresis internal to ICs can be a lot better, because you can
localize the positive feedback into a very tight, single-pole loop.
The HC14 type schmitts are apparently immune from teasing, too.

Opamps often make better comparators than comparators, because they
have one dominant pole and don't store as much information as the
usual fast-multistage comparator topology.

It's funny that the common comparator-plus-hysteresis circuit is
almost universally taught as being a clever thing, taught by people
who don't understand it.

John

One thing I don't understand is why you Old Blokes bolloxed on about
comparators with hysteresis and then gave us comparators with
hysterectomies...... and we still have to deal with them.

DNA

 

[Jim Thompson]

One thing I don't understand is why you Old Blokes bolloxed on about
comparators with hysteresis and then gave us comparators with
hysterectomies...... and we still have to deal with them.

DNA

The MC1650/51 has BALLS ;-)

...Jim Thompson

 

[D from BC]

in message

Hysteresis internal to ICs can be a lot better, because you can
localize the positive feedback into a very tight, single-pole loop.
The HC14 type schmitts are apparently immune from teasing, too.

Opamps often make better comparators than comparators, because they
have one dominant pole and don't store as much information as the
usual fast-multistage comparator topology.

It's funny that the common comparator-plus-hysteresis circuit is
almost universally taught as being a clever thing, taught by people
who don't understand it.

John

One thing I don't understand is why you Old Blokes bolloxed on
about
comparators with hysteresis and then gave us comparators with
hysterectomies...... and we still have to deal with them.

DNA
-------------------
Great! Looks like this cct. is a "sports car" of hysteretic
compartors.

I'm now more suspicious of app notes. Trust nothing.

Got curious and looked up the MC1650.. Dual A/D converter??..
Huhhh...Still have alot to learn.. Internally it's in the
design "ball park" of interest.

Op amps make better comparators!! Looks like I picked up a
myth..In my internet travels, I recall reading that comparators
are best in comparator applications..
I haven't yet compared op-amp/comp internals and specs.
Just blindly running on rumour..
It's a good thing I don't design life support systems

My next move is to take a look at the various IC's containing a
combo of op amps (or comparators) and a D latch to make a
hysteretic comparator.
CMOS would be nice..

Thanks for the verification..
D
------

 

[Genome]

The MC1650/51 has BALLS ;-)

...Jim Thompson
--

Oh Great

What's the point of having balls if you haven't got the cock to deliver it?
I will not mention the sexual aspect of this stuff........ Mr pico second.

Us thickos want a comparator where we can set the up and down stuff about
the somewhere else without using our branes.

DNA

 

[D from BC]

"Jim Thompson" <[email protected]>
wrote in
message news:[email protected]...

The MC1650/51 has BALLS ;-)

...Jim Thompson
--

Oh Great

What's the point of having balls if you haven't got the cock to
deliver it?
I will not mention the sexual aspect of this stuff........ Mr
pico second.

Us thickos want a comparator where we can set the up and down
stuff about
the somewhere else without using our branes.

DNA
..
------------
Talking about picoseconds...
I recently came across this speedy op amp with a hysteresis
control pin.
http://www.analog.com/UploadedFiles/Data_Sheets/ADCMP566.pdf
Interesting but wayyy too fast.
Slower variants are available.
My app specs are 200nS prop delay and 100mV hysteresis.

D

 

[Jim Thompson]

in message

On Wed, 03 Jan 2007 07:57:54 -0800, John Larkin
[snip]
This can be a lot better, because there's no delay coming back around
into a positive-feedback node, and because the comparator prop delays
are effectively pipelined... everything flows left-to-right. The
comparators still have to be well behaved and well characterized,
specifically to have fairly symmetric rising and falling edge prop
delays. But this configuration has fewer screwup modes.

The other nice thing here is that the two comparator references can be
programmed with DACs, allowing thresholds and hysteresis to be under
software control. I use this configuration in my tachometer
conditioning modules, and it's very flexible.

John


Then there's the optimum method I devised in my MC1650/51 design in
the mid '60's ;-)

...Jim Thompson

Hysteresis internal to ICs can be a lot better, because you can
localize the positive feedback into a very tight, single-pole loop.
The HC14 type schmitts are apparently immune from teasing, too.

Opamps often make better comparators than comparators, because they
have one dominant pole and don't store as much information as the
usual fast-multistage comparator topology.

It's funny that the common comparator-plus-hysteresis circuit is
almost universally taught as being a clever thing, taught by people
who don't understand it.

John

One thing I don't understand is why you Old Blokes bolloxed on
about
comparators with hysteresis and then gave us comparators with
hysterectomies...... and we still have to deal with them.

DNA
-------------------
Great! Looks like this cct. is a "sports car" of hysteretic
compartors.

I'm now more suspicious of app notes. Trust nothing.

Got curious and looked up the MC1650.. Dual A/D converter??..

I didn't name it. Back in those days Motorola had a department that
did data sheets. I think the name derived from the 64-wide version I
made for WPAFB for a flash converter.

Huhhh...Still have alot to learn.. Internally it's in the
design "ball park" of interest.

Yep. My 1965 speed numbers compare favorably with today's designs.

Op amps make better comparators!! Looks like I picked up a
myth..In my internet travels, I recall reading that comparators
are best in comparator applications..

I think it's a myth too.

I haven't yet compared op-amp/comp internals and specs.
Just blindly running on rumour..
It's a good thing I don't design life support systems

My next move is to take a look at the various IC's containing a
combo of op amps (or comparators) and a D latch to make a
hysteretic comparator.
CMOS would be nice..

Thanks for the verification..
D
------

I've done several comparator plus D-latch (or even S-R) versions in
CMOS.

But they're custom ASIC's.

...Jim Thompson

 

[Zak]

I've done several comparator plus D-latch (or even S-R) versions in
CMOS.

But they're custom ASIC's.

There's always the 555


Thomas

 

[[email protected]]

I've seen various hysteresis circuits in app notes such as:
http://pdfserv.maxim-ic.com/en/an/AN3616.pdf

I'm not sure how well the circuit with the mosfet steering will work.
At some point, both fets will be on.

I'm not familiar with this method:

The signal is applied to 2 comparators (no feedback) which are
connected to a D type latch.
(Longer discription by request.)

I'd like the longer description.

 

[D from BC]

In regards to using the 555 as a hysteresis comparator....

The 555 is a great suggestion.
I'm somewhat stuck using those internal resistors.
But that might turn out ok...Will be checking specs.
Nationals LinMos sounds like an improvement to the 555.
It's one of the few IC's I know of with comparators and a latch.
D

 

[D from BC]

As requested, longer description for 2 comparator & latch cct to
make a hysteresis comparator.

1) Apply same signal to + on one comparator and - on the other.
2) Apply voltage references to remaining inputs
3) The "valley" comparator output connects to D and reset of the
latch
4) The "peak" comparator output connects to Clk and Set of the
latch
(Even longer description by request )

Kinda like the 555.
D

 

[[email protected]]

As requested, longer description for 2 comparator & latch cct to
make a hysteresis comparator.

1) Apply same signal to + on one comparator and - on the other.
2) Apply voltage references to remaining inputs
3) The "valley" comparator output connects to D and reset of the
latch
4) The "peak" comparator output connects to Clk and Set of the
latch
(Even longer description by request )

Kinda like the 555.
D

Which comparator is peak and valley. [Non-inverting and inverting?] Do
I need to know what is dominant (set versus reset, etc.).

I really don't like a comparator driving the CLK unless the rise/fall
times are known to be fast enough not to cause problems.

The other thing to consider is many circuits these days run
synchronous, so the comparator can just be sampled with a DFF based on
the master clock. I'm not sure if I'm explaining this well.

 

[D from BC]

As requested..
Updated description for the 2 comparator&D type latch hystersis
comparator cct.

A signal is applied to + input of a comparator. This is the
"peak" comparator. It's output connects to Clk and Set of the
latch. The - input gets a ref voltage.

Same signal is applied to the - of another comparator.
This is the "valley" comparator and its output connects to D and
reset of the latch. The + input gets a ref voltage.

For conserns of comparators driving latches:
There's comparators with 1.2nS rise and fall times..
Hopefully good enough...

In my original post, I mentioned that I'm not familiar with this
means of creating a hysteretic comparator..
I haven't thought about the timing to the latch yet.
I'll be examining this circuit further once I've eliminated
other competing methods.

About the sampled comparator& mater clock...
Sorry, too foggy for me..dunno..
I seen comparators with build in hold functions..

D

 

[John Larkin]

As requested, longer description for 2 comparator & latch cct to
make a hysteresis comparator.

1) Apply same signal to + on one comparator and - on the other.
2) Apply voltage references to remaining inputs
3) The "valley" comparator output connects to D and reset of the
latch
4) The "peak" comparator output connects to Clk and Set of the
latch
(Even longer description by request )

Kinda like the 555.
D

You can do the same thing with a simple SR latch (cross-coupled NAND
gates) if you get the comparator polarities right.

If upper comparator says sig>hilim, set the latch.

If lower comparator says sig<lolim, clear it.

In the middle, leave it alone.

John

 

[Jim Thompson]

In regards to using the 555 as a hysteresis comparator....

The 555 is a great suggestion.
I'm somewhat stuck using those internal resistors.
But that might turn out ok...Will be checking specs.
Nationals LinMos sounds like an improvement to the 555.
It's one of the few IC's I know of with comparators and a latch.
D

A variety of noise-blanking circuits using S-R Flops or the 555
equivalent are shown in an old posting at....

http://analog-innovations.com/SED/NoiseBlank.pdf

I used a device equivalent of the last circuit to "shield" automotive
ignition pickups from spark noise in 1968.

...Jim Thompson

 

[D from BC]

Conserning use of comparators and SR latchs to make a hysteresis
comparator..

I'm keeping an eye on that SR latch idea..
The SR latch has that illegal input state (race condition).
My spec is 100mV of hysteresis and this circuit is part of a
smps controller..
Could be like finding a quiet spot in a noisey dance club

I suspect as hysteresis approachs 0 there's more probability
that the SR latch gets simultaneous S and R signals due to noise
presented to the comparators. Just getting scared by this quirk,
but I won't rule it out yet..

I had to review my latch operation and found:
http://www.allaboutcircuits.com/vol_4/chpt_10/4.html
Which describes the D latch without illegal states.

For choice of latch in the circuit...
Perhaps SR is good for wide hystersis and clean signals and D
latch for small hysteresis and dirty signals??

D

 

[D from BC]

Conserning
http://analog-innovations.com/SED/NoiseBlank.pdf

Cooooll...to see the good ol'555 not used as an oscillator..

Thanks
D