How is the wire routed on this evaluation board

[Chengjun Li]

I am now working on designing an evaluation board for a capacitve read out chip since the board is no longer fabricated by the manufacture. The board is used to measure extremely small capacitance difference between external capacitors. The picture of the board is shown below.

I am not sure how the wire is routed on the highlighted area of the board.

It seems SI pin on the chip is connected to a via to the left. Then the signal goes to the bottom of the board,from there I guess it is further connected to the via under the third pin of the op amp in the highlighted area. And then connected to the hole SI to the left edge of the board. There is a wide trace as you can see, to the right the trace is isolated from and stop at the first via mentioned above, and to the left it first connects to the first two pins of the op amp and then connects to the two holes on top and bottom of the hole SI.

1. Is my description of the connection correct?
2. If I am correct, what's the purpose of the wide trace？Is it for reduce the noise from parasitic capacitance?how does it work?



The schematic is shown below with the same region highlighted.

 

[davenn]

I am not sure how the wire is routed on the highlighted area of the board.

well my first obvious Q is ... why are you worried about a N/C ( no connection) pin ??
what makes you think a N/C pin is actually being used ?


Dave

 

[Chengjun Li]

well my first obvious Q is ... why are you worried about a N/C ( no connection) pin ??
what makes you think a N/C pin is actually being used ?


Dave

?? I am not worried about N/C pin. All I concerned is the SI pin. I want to know how is the trace coming out of SI pin routed.

 

[davenn]

yeah OK ... misinterpreted your drawing

sooo do you get a short cct between the 2 via's ?
if so, what is the problem ?

what is the part # for the 8 pin IC ?

 

[Chengjun Li]

yeah OK ... misinterpreted your drawing

sooo do you get a short cct between the 2 via's ?
if so, what is the problem ?

I don't have the evaluation board in my hand, I am trying to infer the wire connection and build a evaluation board based on the picture and schematic. I guess the 2 vias are shorted. But I am not sure because the wire connection is very strange in this region. For example, the wide trace,to the right it stop at a via and connects to nowhere, to the left it connects to two holes which connects to nothing. Isn't this strange?

 

[davenn]

For example, the wide trace,to the right it stop at a via and connects to nowhere, to the left it connects to two holes which connects to nothing. Isn't this strange?

its also connects to the lower left 2 pins of that 8 pin chip ... and the circuit diagram shows that
hence why I asked you ... what that chip is ?


Dave

 

[Chengjun Li]

its also connects to the lower left 2 pins of that 8 pin chip ... and the circuit diagram shows that
hence why I asked you ... what that chip is ?


Dave

That 8 pin chip is an op amp LMC6482. Do you know what's the purpose of wide trace,why it stops at a via to the right? Why it connects to 2 holes on the left, can the two holes be replaced by solid pad or by nothing just leave that area with out adding any component?

 

[davenn]

Do you know what's the purpose of wide trace,why it stops at a via to the right?

it has no specific purpose stopping there, other than it cant go any further
its not uncommon for tracks on PCB's to do that sort of thing


Dave

 

[davenn]

can the two holes be replaced by solid pad or by nothing just leave that area with out adding any component?

not sure what you mean by that ? .... the middle home needs to stay separate ... there's no reason to change the layout from the way it is
if you are doing a replacement board

 

[gorgon]

The signal to SI is routed below the reference/ guard signal on an inner layer, as I've tried to show in the picture. This is if you can't see it on the solder (reversed) side. Due to your question, I think this is a correct assumption.

I suppose your PCB has at least 4 layers, and if you are lucky the inner layers are mostly power planes, but you never know.

 

[garublador]

I agree with gorgon's analysis. To elaborate a bit, they wanted the signal from that SI pin to be strongly coupled to the net that goes to pins 4 and 6 of the connector and pins 1 and 2 of the op amp. It's probably on an adjacent layer at a specific distance with a specific width to get a specific impedance between those two nets.

 

[Chengjun Li]

I agree with gorgon's analysis. To elaborate a bit, they wanted the signal from that SI pin to be strongly coupled to the net that goes to pins 4 and 6 of the connector and pins 1 and 2 of the op amp. It's probably on an adjacent layer at a specific distance with a specific width to get a specific impedance between those two nets.

I think you are right. But isn't a two layer board enough for this? SI net can be placed on the bottom layer.

 

[garublador]

I think you are right. But isn't a two layer board enough for this? SI net can be placed on the bottom layer.

Perhaps. It would depend on what impedance you want between those lines and whether or not it's feasible to get that impedance with a 2 layer board.

 

[gorgon]

I think you are right. But isn't a two layer board enough for this? SI net can be placed on the bottom layer.

If you have a photo of the solder side you can see the SI signal if it is only 2 layers.
The reason I suspect it is a 4 layer PCB is the isolated via(s) on the top plane. This indicate a connection to an inner layer, but again, look at the solder side to be certain.

 

[Chengjun Li]

If you have a photo of the solder side you can see the SI signal if it is only 2 layers.
The reason I suspect it is a 4 layer PCB is the isolated via(s) on the top plane. This indicate a connection to an inner layer, but again, look at the solder side to be certain.

Actually this is the only photo I have. I think you are right. Because I imitate the layout of the top layer using Altium Designer, if it's a two layer board, the routing on the bottom layer will be very messy.

I still have a question if it's a four layer board. As you can see on the right lower corner of the PCB, there are two grounds, GND and FG, which can be connected through a jumper. It seems on the top layer, the GND is restricted to a small region while FG occupies most of the area of the top layer.
And you can see some isolated vias in the FG region which I suppose connect the top layer to the bottom layer. So the bottom layer is also FG. The inner two layers are VCC and GND. In this case, there will only be one GND layer which I think might not be a good idea since usually we have two GND layers(top and bottom) in two layer board. Do you think this is acceptable for a board used to measure very tiny capacitance?

 

[dorke]

It looked familiar to me.
A forum search indeed confirmed that.
Once through the door the other through the window....here

 

[Chengjun Li]

View attachment 23885

The signal to SI is routed below the reference/ guard signal on an inner layer, as I've tried to show in the picture. This is if you can't see it on the solder (reversed) side. Due to your question, I think this is a correct assumption.

I suppose your PCB has at least 4 layers, and if you are lucky the inner layers are mostly power planes, but you never know.

Hi gorgon, I got the picture of the bottom side of the evaluation board from the manufacture. Exactly as you said, I can't see the signal to SI on the bottom side, so it should be a four layer board, the inner two layers are VCC and GND. I also noticed that there is again a reference/guard signal on the bottom side.


Here I have several further questions, 1. which inner layer should I route the signal to SI on, VCC or GND?
2. Should VCC be the second layer right under the top layer?
3. If I route the signal to SI on one inner layer, should I also place a reference/guard signal on the other inner layer?

Thanks in advance.

 

[gorgon]

Sorry for the delay.
If the inner layer is only power and ground, I don't think it is necessary to add any guard ring there. Since you have the guard / reference signal routed on the solder side of the pcb,
I think you should remove any power plane directly between the top and bottom reference/ guard s. This way it is only the signal itself that is between the guard layers.