Hans Camenzind's Book, Designing Analog Chips

[Winfield Hill]

Check out Hans Camenzind's (free, downloadable) book....
http://www.arraydesign.com/designinganalogchips.pdf

New URL, http://www.arraydesign.com/downloads/index.html

Hans' book is out in print now. I received my copy last
week, and I must say, it's far superior to hold it in your
hand than to read it onscreen. Anyway, it's a great book,
very entertaining while informative, good illustrations,
highly recommended. Low cost as well, $21.95 or $15.99.
http://www.amazon.com/gp/product/1589397185/104-3765969-1930304

 

[Joerg]

Hello Winfield,

Hans' book is out in print now. I received my copy last
week, and I must say, it's far superior to hold it in your
hand than to read it onscreen. ...

Thanks, using PDF to study a topic like that gets old and so do the
eyes. Books will always have their place. Like AoE which I can't imagine
to ever use in electronic form, it's too much information for that. I
like Hans' style, and that he offers brief histories of inventors. It
really hadn't sunk in for me that Robert Noyce died so young. The last
portion of the story about William Shockley gave me goose pimples.

The claim about there being more MOS transistors than ants, I don't
know. Maybe Hans has never witnessed a termite infestation.

Win, what do you think of their 700 series semi-custom bipolar offering?
It all looks enticing and with the large number of cross-unders a single
metal layout shouldn't be much of a sweat. The only thing I don't like
is the fact that there is only one kind of resistor and it's only
750ohms. That kind of slams the door for most of my designs. There would
have to be a gazillion of those to make low power circuitry feasible but
there aren't.

Regards, Joerg

 

[Jim Thompson]

Hello Winfield,



Thanks, using PDF to study a topic like that gets old and so do the
eyes. Books will always have their place. Like AoE which I can't imagine
to ever use in electronic form, it's too much information for that. I
like Hans' style, and that he offers brief histories of inventors. It
really hadn't sunk in for me that Robert Noyce died so young. The last
portion of the story about William Shockley gave me goose pimples.

The claim about there being more MOS transistors than ants, I don't
know. Maybe Hans has never witnessed a termite infestation.

Win, what do you think of their 700 series semi-custom bipolar offering?
It all looks enticing and with the large number of cross-unders a single
metal layout shouldn't be much of a sweat. The only thing I don't like
is the fact that there is only one kind of resistor and it's only
750ohms. That kind of slams the door for most of my designs. There would
have to be a gazillion of those to make low power circuitry feasible but
there aren't.

Regards, Joerg

I fitted a couple of designs onto the analog arrays... at customer
insistence, then gave it up. MOSIS pretty much eliminates the need.

...Jim Thompson

 

[Winfield Hill]

Joerg wrote...

Win, what do you think of their 700 series semi-custom bipolar offering?
It all looks enticing and with the large number of cross-unders a single
metal layout shouldn't be much of a sweat. The only thing I don't like
is the fact that there is only one kind of resistor and it's only
750ohms. That kind of slams the door for most of my designs. There would
have to be a gazillion of those to make low power circuitry feasible but
there aren't.

I didn't find it very appealing in the several look-sees I gave
it over the years. I'll bet even Hans didn't use it much.

 

[Joerg]

Hello Jim,

I fitted a couple of designs onto the analog arrays... at customer
insistence, then gave it up. MOSIS pretty much eliminates the need.

Yes, but that requires a full blown (and expensive) IC design. For
really simple stuff it would be nice to live with what's provided and do
the metal layout. Just like with gate arrays in the digital world. If
they just hadn't limited it to 750ohm resistors.

Regards, Joerg

 

[Joerg]

Hello Win,

I didn't find it very appealing in the several look-sees I gave
it over the years. I'll bet even Hans didn't use it much.

Thanks, almost thought so and Jim didn't sound too enthused either. Is
there something better out there? Something with higher value resistors?

Regards, Joerg

 

[Robert]

Hello Win,


Thanks, almost thought so and Jim didn't sound too enthused either. Is
there something better out there? Something with higher value resistors?

Regards, Joerg

I've mentioned Maxim's Quickchip Analog Array they got from Tektronix when
they purchased their IC processes back a few years.

http://www.maxim-ic.com/products/asics/fiber/design_methods.cfm

In: http://www.maxim-ic.com/products/asics/images/QC9.pdf

they mention:

The QuickChip 9-60D consists of a 36-pad die, 75 by 70 mils (1.91 x 1.78mm)
in size, with 3,790
devices arrayed into different tiles optimized for various analog or digital
designs. The analog sec-
tion consists of 6 core tiles, 4 large NPN tiles, 2 bias tiles, 9 I/O tiles,
and 1 tile optimized for use as
a VCO with a combined total of 484 NPN transistors, 164 lateral PNP
transistors, 114 Schottky
diodes, 1,218 resistors (>2.4M? total), and 140 capacitors (74pF total).
Area is available for cus-
tom nichrome resistors in or near each analog tile. The digital section
consists of 14 digital tiles
(each capable of implementing a clocked master-slave data latch) and 3
digital I/O tiles for both
ECL and TTL I/O. Diodes are provided at each bond pad along with 3 prewired
supply shunts to
protect your design from ESD. Collectively, this QuickChip contains 1,022
NPN transistors, 176 lat-
eral PNP transistors, 426 diodes, 2,008 poly resistors (>6.8M?), and 158
capacitors (116pF total).
Fabricated on the GST-2 process, QuickChip 9 uses a 3-layer metal
interconnect system for high cir-
cuit density and low interconnect capacitance. The first and second layers
employ a 2.7µm pitch
metal for signal interconnect while the 5.4µm pitch third layer metal is
typically used for power sup-
ply routing. Unlike many IC processes, GST-2's metal system uses plated gold
for high reliability and
low resistance. For precision circuits, trimmable resistors are available

Can't tell what the prices might be but I thought they had a pizza mask with
multiple customer designs that ran every once in a while for a reduced cost.

Robert

 

[Jim Thompson]

Hello Jim,


Yes, but that requires a full blown (and expensive) IC design. For
really simple stuff it would be nice to live with what's provided and do
the metal layout. Just like with gate arrays in the digital world. If
they just hadn't limited it to 750ohm resistors.

Regards, Joerg

Naaah. A MOSIS run is quite cheap. Each process has a "shuttle"
run... multiple chip designs on a single wafer. Good cheap way for
"proof of pudding".

As for arrays, I designed one for GenRad internal use that had more
values, but it didn't see much use either.

And I might add... he who complains about resistor values shouldn't be
trying to design an I/C ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

Anyone can be rude, but it takes a Democrat to be a real dirtbag.

 

[Keith Williams]

Naaah. A MOSIS run is quite cheap. Each process has a "shuttle"
run... multiple chip designs on a single wafer. Good cheap way for
"proof of pudding".

As for arrays, I designed one for GenRad internal use that had more
values, but it didn't see much use either.

And I might add... he who complains about resistor values shouldn't be
trying to design an I/C ;-)

In the '70s I did circuit designs on logic gate arrays. The
resistors were all fixed and weird values. Most of the time it
didn't much matter, but there were some strange parallel/series
networks to get close. Fast stuff though[*], at least for the era.

[*] It was *really* fast when I started my simulations. A cow-
orker had divided all the capacitors in the standard model by 1E3.

 

[Joerg]

Hello Jim,

Naaah. A MOSIS run is quite cheap. Each process has a "shuttle"
run... multiple chip designs on a single wafer. Good cheap way for
"proof of pudding".

The run isn't so expensive but there you have to do the full chip design
from scratch. I know that this is your bread and butter but many times
my clients shy away from that because of the design costs. If it were
just one or two metal mask layouts it might be easier to convince them.

And I might add... he who complains about resistor values shouldn't be
trying to design an I/C ;-)

Well, I am not complaining about tolerances since you can do ratios.
It's ok if they are 30% or whatever but low power designs require at
least one type in the 1M range. Dividers for low battery detect, other
thresholds and so on. Can't do current sources everywhere, plus they eat
from the rather small pool of NPN/PNP.

Regards, Joerg

 

[Joerg]

Hello Robert,

I've mentioned Maxim's Quickchip Analog Array they got from Tektronix when
they purchased their IC processes back a few years.

http://www.maxim-ic.com/products/asics/fiber/design_methods.cfm

In: http://www.maxim-ic.com/products/asics/images/QC9.pdf

Yes, that's another option. However, there are only a couple of 100K
while the others are small. Nothing above 100K. Typically a chip design
can live without but there are situations in the low power world where
you can't. The old LM331 is an example. If you cant to do something like
this in a low power environment you can't do the timer comparator
divider with 100K.

Regards, Joerg

 

[Jim Thompson]

Hello Jim,


The run isn't so expensive but there you have to do the full chip design
from scratch. I know that this is your bread and butter but many times
my clients shy away from that because of the design costs. If it were
just one or two metal mask layouts it might be easier to convince them.


Well, I am not complaining about tolerances since you can do ratios.
It's ok if they are 30% or whatever but low power designs require at
least one type in the 1M range. Dividers for low battery detect, other
thresholds and so on. Can't do current sources everywhere, plus they eat
from the rather small pool of NPN/PNP.

Regards, Joerg

When the customer will allow it I'm fond of allotting a pin for an
external current-set resistor. Then ratio everything internally from
that reference current.

...Jim Thompson

 

[Joerg]

Hello Jim,

When the customer will allow it I'm fond of allotting a pin for an
external current-set resistor. Then ratio everything internally from
that reference current.

With current sense I'd always try to go that route as well. But when you
have to register half a dozen voltage thresholds leaving the resistors
outside can get old. Many times we decide to leave things discrete.

Even on the new MSP430F2xxx family TI had mercy and gave us four Hi-Ohms
resistors to do the battery detect on chip. Plus some others to control
the ring oscillator and so on. Some of us had sent the a "Dear Santa"
list and lo and behold almost all of my items made it in there. Could
win them a design-in this time if they honor the negotiated price.

In the market for those kinds of uC they duke it out in the sub microamp
range. 1-2uA too much can blow you right out of the water.

Regards, Joerg

 

[Chris Jones]

Hello Jim,


The run isn't so expensive but there you have to do the full chip design
from scratch. I know that this is your bread and butter but many times
my clients shy away from that because of the design costs. If it were
just one or two metal mask layouts it might be easier to convince them.

I reckon the layout would be much easier if you use MOSIS since then you are
not stuck with the component placement you get, you are free to move stuff.
Also you'll get several real metal layers so you don't have to mess around
with resistive cross-unders. If ESD performance is very important to you
then you might need to ask someone experienced to show you how to do ESD
cells for the IO pads, but the rest of the chip should be quite simulatable
and predictable. You'd need some decent models which I think you would get
under NDA with MOSIS, and you'd need some software too.

Well, I am not complaining about tolerances since you can do ratios.
It's ok if they are 30% or whatever but low power designs require at
least one type in the 1M range. Dividers for low battery detect, other
thresholds and so on. Can't do current sources everywhere, plus they eat
from the rather small pool of NPN/PNP.

More reason to go MOSIS. You need to think about the total resistance in
your circuit, so having one 1M resistor is a reasonable proposition, but
asking for 20 of them is being greedy since for high value resistors
(minimum width), the chip area is proportional to the resistance value.

Chris

 

[Joerg]

Hello Chris,

I reckon the layout would be much easier if you use MOSIS since then you are
not stuck with the component placement you get, you are free to move stuff.
Also you'll get several real metal layers so you don't have to mess around
with resistive cross-unders. ...

True. But for simple circuits I'd be happy with fixed placement and
cross-unders (provided there are enough of these). It's like gate arrays
versus ASIC. A lot of times we did gate arrays, produced for a couple
years or so and then had someone pour it into an ASIC. But that was
because of the rather high cost of gate arrays, something that isn't
true for discrete analog circuitry anymore.

More reason to go MOSIS. You need to think about the total resistance in
your circuit, so having one 1M resistor is a reasonable proposition, but
asking for 20 of them is being greedy since for high value resistors
(minimum width), the chip area is proportional to the resistance value.

Yes, they do eat real estate. I just wonder how a 'chip in a can'
program can be successful these days with only 750ohm resistors. Lots of
stuff needs to operate on little coin cells and that just won't work
without high-Z dividers.

Maybe that's one reasons why many of my discrete designs are never
transferred to chips although I always try to design stuff in a way that
it would suit a CMOS or bipolar process. Clients usually say that the
NRE for the design are too high and the chip designers claim that's
because the SW tools are so expensive (which they probably are). It was
different 20 years ago but nowadays the assembly of a discrete board has
become so cheap that the NRE for a chip wouldn't amortize.

Regards, Joerg

 

[Jim Thompson]

New URL, http://www.arraydesign.com/downloads/index.html

Hans' book is out in print now. I received my copy last
week, and I must say, it's far superior to hold it in your
hand than to read it onscreen. Anyway, it's a great book,
very entertaining while informative, good illustrations,
highly recommended. Low cost as well, $21.95 or $15.99.
http://www.amazon.com/gp/product/1589397185/104-3765969-1930304

Well... Three things...

Now we know why the book is only $21.95 ;-)

Wonder how he "introduced the phase-locked loop concept to ICs"?
Motorola was making PLL chips designed by Ron Treadway and myself
before Hans left graduate school.

"In February of 1964 David Hilbiber of Fairchild..." discovered the
concept of what would later develop into bandgaps. Six years later
(1970) "...Bob Widlar put in the missing pieces".

Except I was making bandgaps well before I left Motorola in 1970.
Guess that'll teach me to publish instead of just going for the big
bucks ;-)

...Jim Thompson

 

[Glen Walpert]

Well... Three things...

Now we know why the book is only $21.95 ;-)

Wonder how he "introduced the phase-locked loop concept to ICs"?
Motorola was making PLL chips designed by Ron Treadway and myself
before Hans left graduate school.

"In February of 1964 David Hilbiber of Fairchild..." discovered the
concept of what would later develop into bandgaps. Six years later
(1970) "...Bob Widlar put in the missing pieces".

Except I was making bandgaps well before I left Motorola in 1970.
Guess that'll teach me to publish instead of just going for the big
bucks ;-)

...Jim Thompson

Interesting two things, but these history errors would not seem to
relate much to the books usefulness to someone wishing to learn analog
IC design. And it would be a bit much to expect it to be of much use
to an old pro like you, but is it useful in its presentation of design
methodology for the newbie, without being too misleading or outdated?

 

[Jim Thompson]

Interesting two things, but these history errors would not seem to
relate much to the books usefulness to someone wishing to learn analog
IC design. And it would be a bit much to expect it to be of much use
to an old pro like you, but is it useful in its presentation of design
methodology for the newbie, without being too misleading or outdated?

It's passable, but there are a lot of no-no's... see Fig. 5-12 and
mull over it for awhile.

...Jim Thompson

 

[Fred Bloggs]

Well... Three things...

Now we know why the book is only $21.95 ;-)

It's just a pamphlet that he describes as an "overview." It's not meant
to be all encompassing. Camenzind already has two other mainstream
textbooks to his credit. The main purpose of this latest is to simply
convey a perspective and assumes a working knowledge of electronics. And
as for the alleged historical inaccuracies, if the work was proprietary
and not made available to the industry, it did not exist. An independent
discovery that did not rely on the ground breaking achievements you
claim is a discovery nonetheless, and, if it was published, the credit
for that discovery *rightfully* goes to that author. Therefore,
Camenzind's historical narratives are absolutely correct, accurate, and
without error; this is *the* history of electronics development, and you
have been left out. This book is a significant contribution and
resource, well worth the money.

 

[Glen Walpert]

On Thu, 23 Feb 2006 00:19:53 GMT, Glen Walpert wrote:


It's passable, but there are a lot of no-no's... see Fig. 5-12 and
mull over it for awhile.

...Jim Thompson

Chapter 5 made good sense to me right up to 5-12, "Self starting
current source without large value resistors". Alas, I am unable to
understand this circuit well enough to guess what the no-no is. He
says the purpose is to eliminate wasted power by replacing the
"primary current" from Vcc in 5-14 with current the circuit is
intended to generate, I1. If Vcc in fig 5-12 is replaced by I1 and Q4
eliminated entirely, the figure might seem to accomplish that. ???