fet for automatic gain control?

[Hul Tytus]

sci.electronics.design
fet for automatic gain control?

Thanks for all the suggestions. Trying the 2n7000, or similiar device, appears
the best bet at this point and see what happens.

Hul

 

[dp]

sci.electronics.design
fet for automatic gain control?

Thanks for all the suggestions. Trying the 2n7000, or similiar
device, appears
the best bet at this point and see what happens.

Hul

Hmmm, seems you did not read my reply via comp.arch.embedded.

Does the 2N7000 still look like your best bet after you checked how
much its capacitance D-G is.

JFET-s have been used as variable resistors for ages, depending
on the bandwidth you are after there can be different choices.
Up to a few (tens of) MHz your best option is the 2N4391 (or
the 2N4856, same thing practically).
In my reply via comp.arch.embedded I already told you about
what sort of linearity, temperature drift etc. to expect.

Dimiter

 

[Robert Baer]

Hmmm, seems you did not read my reply via comp.arch.embedded.

Does the 2N7000 still look like your best bet after you checked how
much its capacitance D-G is.

JFET-s have been used as variable resistors for ages, depending
on the bandwidth you are after there can be different choices.
Up to a few (tens of) MHz your best option is the 2N4391 (or
the 2N4856, same thing practically).
In my reply via comp.arch.embedded I already told you about
what sort of linearity, temperature drift etc. to expect.

Dimiter

Do not confuse anyone with factual experience.

 

[[email protected]]

As you say, the enhancement types aren't a good fit. The hooker is that
they do fit and the depletion devices don't - no room for a negative
supply or control mechanism. The board is 2 by 1/2 inches and it's already
filled and bursting.

Hul

 

[[email protected]]

The need for a negative supply or convoluted control circuitry for jfets
excludes them, unfortunantly.

Hul

Hmmm, seems you did not read my reply via comp.arch.embedded.

 

[dp]

Jfets are horrible for repeatability. Idss specs can be 3:1 if you're
lucky, 10:1 on some parts. Enhancement mosfets won't be worse that
that. But any fet-based open-loop attenuator is going to be bad. If
you close a loop around it, an enhancement device, run at low voltage
swings, will work about as well as a jfet.

If you don't care about the noise (times if not orders of magnitude
higher) then a 2N7002 or sort of might do.

Repeatability is not that bad, with the 2N4391 you can rely
on it going down to around 30 Ohm at 0V GS over temp (some will go
well below 20 Ohm at 25C). I know this because I have done variable
gain using FETs 15+ years ago; I had to pair them (no paired 4391,
only 4393 as 2N5566 IIRC) for temperature compensation, to eeprom
calibrate against temperature drift (which was still too high
for a 13 bit ADC), and to digitally linerarize the conversion
results (12 bit INL was OK but with FETs you go into a few % INL,
1% is the best case)...
( http://tgi-sci.com/tgi/21flr.gif - photo taken with the 2N5566,
before the paired 4391 were bulkier and uglier (soldered cans,
http://tgi-sci.com/tgi/21fcr.gif - the companion board,
http://tgi-sci.com/tgi/servo.gif - the servo driven rotary switches,
caps etc. not yet soldered when photo was taken,
http://tgi-sci.com/tgi/21par.gif - boards & servo put together,
http://tgi-sci.com/tgi/m321tb.htm - the still kept historic reference
to the entire mid-90s designed madness).

But since he cannot afford the -10V headroom a 4391 would take
this is a non-issue, either the 2N7002 will do or not.

Dimiter

 

[Phil Hobbs]

Jfets are horrible for repeatability. Idss specs can be 3:1 if you're
lucky, 10:1 on some parts. Enhancement mosfets won't be worse that
that. But any fet-based open-loop attenuator is going to be bad. If
you close a loop around it, an enhancement device, run at low voltage
swings, will work about as well as a jfet.

BF862s are pretty good for that--their transconductance is so high that
they go from completely off to I_DSS in about 400 mV. Also I_DSS is
pretty tightly specified for a FET, 10 mA < I_DSS < 25 mA.

None of this MPF102-ish stuff. (The Fairchild MPS102 datasheet
specifies that at I_D = 200 uA, V_GS is somewhere between -0.5 and -7.5
V. Nice of them.)

An enhancement pHEMT such as an ATF54143 might be a good sub.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[[email protected]]

Standard technique for linearizing a JFET resistive divider is to add 1/2 the AC portion of the drain voltage to the DC gate gain- control voltage (you probably already knew this!). The large-signal performance is still pretty crappy, the log-anti-log technique works better but takes more componentsunless you use an IC. Not sure if this would also work for enhancement-mode.

Bob

 

[dp]

Standard technique for linearizing a JFET resistive divider is to add 1/2
the AC portion of the drain voltage to the DC gate gain- control voltage
(you probably already knew this!).

Oh yes, I knew it. I am not quite sure now (almost 20 years after
my initial design) why I could not use it but I remember I considered
and may be tried it. I think the effect kicked in at larger amplitudes
than I used (about 100mV IIRC is what I used, in that ballpark
anyway), and it did not combine well with the paring for compensation
(soldering the cans shorts the gates so one had to live with that).

The large-signal performance is still pretty crappy, the log-anti-log
technique works better but takes more components unless you use
an IC. Not sure if this would also work for enhancement-mode.

Yes, large signal was out of question. So they had to be low-noise,
the opamps also had to be very quiet (ADI still make them!).
Overall things were not as quiet as they nowadays are but it was
OK, well below 2 channels FWHM at 8k spectrum from the pulser
(nowadays things are well below 1 channel and less mad from the
analog point of view - the madness went mostly digital ...
http://tgi-sci.com/misc/nmc3top.gif , tgi-sci.com/tgi/nmca3.htm ,
http://tgi-sci.com/tgi/nmc3spc.htm#varfddi ).

Dimiter

 

[[email protected]]

Terry - that comes close but, though the gate is within the available
voltage supply, it is backwards relative to the available control
direction; ie, positive for lower resistence, negative for greater.

Hul

Negative supply not needed, just use a P-channel JFET so channel
can be grounded, gate positive for max gain, near ground for
minimum gain.

The following is a LTSPICE circuit for a simple unity-gain limiter
that runs from a single 5V supply and limits the output to about
0.7V RMS. Not super-low distortion when limiting but good for
reducing signals to power amps to protect speakers, etc. R16 sets
the limited output level, R8 sets overall gain (and input resistor
R1 too but don't go too low there), R13 sets attack time, R14 along
with R15+R16 sets release time, C4 affects both attack and release.
R19 and C6 are special sauce to (attempt) to clean up the attack.
A J177 or J176 should work for the JFET (mostly compensates for
varying gate threshold.. for more compensation reduce R18 to 4.7K
to increase control loop gain but then the special sauce gets
trickier), R4 and C5 feeds in the 1/2 channel distortion cancel
signal to the emitter of the control transistor, about 1/2 of R17
minus a bit to compensate for gain loss in the transistor. Any
decent dual opamp will do.. LT1366 used for convenience. Push-pull
config used to detect both positive/negative peaks.

The 2nd to last line is a JFET model, probably will wrap
so unwrap it (TEXT lines need to be one line).