electrical interface problem LVPECL - LVDS multi-inputs

[Kurt Kaiser]

Hi there,

I'm currently having a serious problem: I got an LVPECL clock synthesizer
and I want to connect it to several clock inputs on my FPGA. The FPGA
features 2 LVDS interfaces, whereas each LVDS pair is located at opposite
sides of the device, meaning there will be some extensive routing to do. I
designed a resistor network for the level conversion from LVPECL to LVDS.
What I'd like to know now is
a) Can I route the 2x2 lines (two times differential to the two opposite
sides of the FPGA) one-to-one out of my clock device to the inputs or should
I use a dedicated buffer / repeater IC for clock distribution?
b) If clock buffer are needed, should I use LVPECL buffers and do the
conversion to LVDS level afterwards or should I perfom the conversion before
the buffer and then use an LVDS IC?
c) Where should I place the level conversion network? Is is better to place
it right at the LVPECL output or is it more advisable to do it right before
the FPGA inputs after a transmission line length of about 7 cm?
Any help, comments, advice is highly appreciated!

Thank you all very much.
Kurt

 

[Andy]

Why do you need to connect the same clock to more than one clock input
on your FPGA? What kind of FPGA are you using?

If I had to buffer and translate, I would rather translate, then
buffer. Unless you are very careful with your resistors and
interconnect, a resistor translator may not work too well.

Andy

 

[Kurt Kaiser]

Why do you need to connect the same clock to more than one clock input
on your FPGA? What kind of FPGA are you using?

If I had to buffer and translate, I would rather translate, then
buffer. Unless you are very careful with your resistors and
interconnect, a resistor translator may not work too well.

Andy

Thanks so far for your answer. I'm using Virtex-4 FX60. Depending on the
implemented designs I will use either the clock input on one side or the
other, not both the at the same time of course. So I'm hoping for more
flexibility and freedom of clock routing if I have two clocks available and
stick to the one that fits better from design to design. The FPGA's input is
LVDS.

 

[Andy]

Those clock inputs cannot be configured as LVPECL? I know general
purpose differential inputs can be LVPECL. You have to terminate on
board though.

Are there other things on board clocked off the same clock? If not
(i.e. nothing external is synchronous to that clock somewhere, then
what does it matter which side you get into the FPGA on; just pick one
and build the board that way. I can't imagine the FPGA clock design
would be nearly as complex (or risky) as what you want to do on the
board.

Andy

 

[Gabor]

Those clock inputs cannot be configured as LVPECL? I know general
purpose differential inputs can be LVPECL. You have to terminate on
board though.

My understanding of LVDS inputs is that you have a differential
receiver that switches at the signal crossing point within the
specified timing as long as your common mode voltage is
within the databook spec. I haven't used Virtex-4 yet, but
at least in earlier Xilinx parts the LVDS input common mode
range was broad enough to support LVPECL. This will most
likely depend on the VCCio for that bank. The datasheet
seems to imply that you have the full GND to VCCio range
for signal swing. Common mode range would be less.