G
Geronimo Stempovski
Hi folks,
I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some
periphery. The three FPGAs are needed due to the data processing complexity
and the amount of high-speed IOs (MGTs). What I am most concerned about
right now is to find an appropriate clocking solution.
In my opinion, there are mainly three alternatives to design the clocking
scheme:
a) connection of the clock in a star-like topology, feeding each of the
three FPGAs with the same clock signal (which has to be possibly duplicated
by a clock buffer to generate three out of one clock reference signal,
thereby introducing additional jitter)
b) clock in daisy-chain, feeding each of the three FPGAs with the identical
clock signal which is routed from one device to another (in terms of jitter
this is also not an optimal solution)
c) each FPGA device is supplied with its own clock (which than can be
optimally routed to the device in short distances), but synchronization is a
major issue then
Does anyone have sufficient experience in designing clock trees and is
willing to share his experience, comments, hints and suggestions with me?
Thanks in advance
Gero
I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some
periphery. The three FPGAs are needed due to the data processing complexity
and the amount of high-speed IOs (MGTs). What I am most concerned about
right now is to find an appropriate clocking solution.
In my opinion, there are mainly three alternatives to design the clocking
scheme:
a) connection of the clock in a star-like topology, feeding each of the
three FPGAs with the same clock signal (which has to be possibly duplicated
by a clock buffer to generate three out of one clock reference signal,
thereby introducing additional jitter)
b) clock in daisy-chain, feeding each of the three FPGAs with the identical
clock signal which is routed from one device to another (in terms of jitter
this is also not an optimal solution)
c) each FPGA device is supplied with its own clock (which than can be
optimally routed to the device in short distances), but synchronization is a
major issue then
Does anyone have sufficient experience in designing clock trees and is
willing to share his experience, comments, hints and suggestions with me?
Thanks in advance
Gero