delta sigma dac

[jonpry@gmail.com]

Hi,

I am trying to build a delta-sigma dac using the outputs of an
fpga. I need about 30mhz bandwidth and 8-10 bits. I was going to use
an 8-bit r-2r ladder, but the i/o requirements are huge since i need
16 channels. The maximum output rate of the fpga pins is about 300mhz
which is far to slow to get 8-10 bits@30mhz. If i use a dac larger
than 1-bit could this work. Eg a 4-bit r-2r used in a delta sigma.
Does anyone have the equations for frequency/amount of quantization/
output bandwidth?

Thanks,

Jon Pry

 

[JosephKK]

Hi,

I am trying to build a delta-sigma dac using the outputs of an
fpga. I need about 30mhz bandwidth and 8-10 bits. I was going to use
an 8-bit r-2r ladder, but the i/o requirements are huge since i need
16 channels. The maximum output rate of the fpga pins is about 300mhz
which is far to slow to get 8-10 bits@30mhz. If i use a dac larger
than 1-bit could this work. Eg a 4-bit r-2r used in a delta sigma.
Does anyone have the equations for frequency/amount of quantization/
output bandwidth?

Thanks,

Jon Pry

Classically, 8 to 10 x oversampling will get you 3 additional bits
resolution. CVSD (delta-sigma converters) gives better dynamic range
at lower resolution for the same bit rate. With 16 channels out,
perhaps dedicated DAC chips would be best.