Debouncing....at About 1Mhz

[John Larkin]

I think you guys (JF and JL) are making things to
complicated. At first I though a Flip-Flop was needed
but now I think a single OR gate with a Cap will do
it, as I posted.
Cheap, simple, and fail proof. It "triggers" on the
1st detection of a Hi, so it's fast, then latchs up
for a period decided by the Cap value, and ignores
the rest and then automatically resets.
Regards
Ken

That cleans the input rising edge but propagates all the falling-edge
glitches. I don't think that's compatible with D's first-post
requirements. The output falling edge will be nasty, too, which is
fixable with another resistor.



John

 

[Ken S. Tucker]

That cleans the input rising edge but propagates all the falling-edge
glitches.

No it does not. The OR gate locks up to a
hard Hi O/P 1 then when the O/P goes to
Lo the gate gets a hard "0" via the feed-back
Cap.

I don't think that's compatible with D's first-post
requirements. The output falling edge will be nasty, too, which is
fixable with another resistor.
John

The OP revised his conditions, and said bounce
settles in a fixed time, that my circuit will adjust
to by a variation of the Cap.
Any logarithmic ringing below the Hi threshhold
is ignored, (~ 2/3 Vcc).
Regards
Ken

 

[John Larkin]

No it does not. The OR gate locks up to a
hard Hi O/P 1 then when the O/P goes to
Lo the gate gets a hard "0" via the feed-back
Cap.

But it's an OR gate.

CRAP .or. 0 = CRAP


John

 

[John Fields]

I think you guys (JF and JL) are making things to
complicated. At first I though a Flip-Flop was needed
but now I think a single OR gate with a Cap will do
it, as I posted.
Cheap, simple, and fail proof. It "triggers" on the
1st detection of a Hi, so it's fast, then latchs up
for a period decided by the Cap value, and ignores
the rest and then automatically resets.

 

[JosephKK]

D from BC [email protected] posted to sci.electronics.design:

Ok..if I hairballize your circuit a bit
D from BC

OK here is my suggestion:


5k
20 pF || ___
.-||-o-----|___|- 5v
| || |
| |
__ .-o-----. __
gnd --\ \| .-------------------| \
| | | | )o-
o--------o/__/| | .---|__/ | __
| | | | '-------| \
| | | | | )o-----o
| 9602 | )---------------)---' '--|__/ |
| | | | | | |
| '--o----' | | | |
| | | | '--+ +---'
| | | | \ /
| | | | X
| '--------------------| | / \
| | | .--+ +---.
| | | | |
| | | | |
| 5k | | | __ |
| 20 pF || ___ | | '--| \ |
| .-||-.-----|___|- 5v | | | )o--'
| | || | | | '-----|__/
| | | | | |
| __ .-------. | | |
'----\ \| | __ | | |
| | o-------| \ | | |
5v --o/__/| | | )o--)---)--------'
| | .--|__/ | |
| | | | |
| | | | |
9602 | '----)----------' |
'--o----' | |
| | |
| | |
----------o--------------'










(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)

Now if someone wants to breadboard it or simulate it in spice i would
like to see the results.

 

[Jim Thompson]

D from BC [email protected] posted to sci.electronics.design:




OK here is my suggestion:


5k
20 pF || ___
.-||-o-----|___|- 5v
| || |
| |
__ .-o-----. __
gnd --\ \| .-------------------| \
| | | | )o-
o--------o/__/| | .---|__/ | __
| | | | '-------| \
| | | | | )o-----o
| 9602 | )---------------)---' '--|__/ |
| | | | | | |
| '--o----' | | | |
| | | | '--+ +---'
| | | | \ /
| | | | X
| '--------------------| | / \
| | | .--+ +---.
| | | | |
| | | | |
| 5k | | | __ |
| 20 pF || ___ | | '--| \ |
| .-||-.-----|___|- 5v | | | )o--'
| | || | | | '-----|__/
| | | | | |
| __ .-------. | | |
'----\ \| | __ | | |
| | o-------| \ | | |
5v --o/__/| | | )o--)---)--------'
| | .--|__/ | |
| | | | |
| | | | |
9602 | '----)----------' |
'--o----' | |
| | |
| | |
----------o--------------'










(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)

Now if someone wants to breadboard it or simulate it in spice i would
like to see the results.

That's the classic approach. IIRC there is a version that somehow
gets both positive and negative edge triggers from a single 9602.

I also don't know if the 9602 can handle the fast edges that "D from
BC" mentions.

...Jim Thompson

 

[D from BC]

That's the classic approach. IIRC there is a version that somehow
gets both positive and negative edge triggers from a single 9602.

I also don't know if the 9602 can handle the fast edges that "D from
BC" mentions.

...Jim Thompson

The lower the tp ...the more I can increase the frequency in my app.
<10nS might be getting exotic but I can accept delays up to an
absolute max of 100nS.
But around 100nS...it's just ho-hum.. Yawn :O
But ...in the 10nS neighborhood..things get exciting.
That's probably why I posted <10nS instead of posting (<100nS).


D from BC

 

[Jim Thompson]

The lower the tp ...the more I can increase the frequency in my app.
<10nS might be getting exotic but I can accept delays up to an
absolute max of 100nS.
But around 100nS...it's just ho-hum.. Yawn :O
But ...in the 10nS neighborhood..things get exciting.
That's probably why I posted <10nS instead of posting (<100nS).


D from BC

I suspect the cleanest approach would be two D-flops that catch the
first occurrence of a transition (positive or negative) and cross-lock
in some fashion to accomplish the "blanking interval"... neither one
having to try to follow the vigorous ringing.

...Jim Thompson

 

[John Larkin]

D from BC [email protected] posted to sci.electronics.design:




OK here is my suggestion:


5k
20 pF || ___
.-||-o-----|___|- 5v
| || |
| |
__ .-o-----. __
gnd --\ \| .-------------------| \
| | | | )o-
o--------o/__/| | .---|__/ | __
| | | | '-------| \
| | | | | )o-----o
| 9602 | )---------------)---' '--|__/ |
| | | | | | |
| '--o----' | | | |
| | | | '--+ +---'
| | | | \ /
| | | | X
| '--------------------| | / \
| | | .--+ +---.
| | | | |
| | | | |
| 5k | | | __ |
| 20 pF || ___ | | '--| \ |
| .-||-.-----|___|- 5v | | | )o--'
| | || | | | '-----|__/
| | | | | |
| __ .-------. | | |
'----\ \| | __ | | |
| | o-------| \ | | |
5v --o/__/| | | )o--)---)--------'
| | .--|__/ | |
| | | | |
| | | | |
9602 | '----)----------' |
'--o----' | |
| | |
| | |
----------o--------------'

A fast input spike can fire both one-shots! Then the fun begins.

John

 

[D from BC]

D from BC [email protected] posted to sci.electronics.design:




OK here is my suggestion:


5k
20 pF || ___
.-||-o-----|___|- 5v
| || |
| |
__ .-o-----. __
gnd --\ \| .-------------------| \
| | | | )o-
o--------o/__/| | .---|__/ | __
| | | | '-------| \
| | | | | )o-----o
| 9602 | )---------------)---' '--|__/ |
| | | | | | |
| '--o----' | | | |
| | | | '--+ +---'
| | | | \ /
| | | | X
| '--------------------| | / \
| | | .--+ +---.
| | | | |
| | | | |
| 5k | | | __ |
| 20 pF || ___ | | '--| \ |
| .-||-.-----|___|- 5v | | | )o--'
| | || | | | '-----|__/
| | | | | |
| __ .-------. | | |
'----\ \| | __ | | |
| | o-------| \ | | |
5v --o/__/| | | )o--)---)--------'
| | .--|__/ | |
| | | | |
| | | | |
9602 | '----)----------' |
'--o----' | |
| | |
| | |
----------o--------------'










(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)

Now if someone wants to breadboard it or simulate it in spice i would
like to see the results.

If I have this right...
4 device delays for neg edge.
4 device delays for pos edge.

IIRC, the JL cct only has a 2 device delay.


D from BC

 

[Jim Thompson]

This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|


Out +------------------------+
| |
A' B'
-------+ +-------------


Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind sharing..let
me know a topology...

In the meantime, I'll be doodling until I get a solution...


D from BC

My thoughts....

http://www.analog-innovations.com/SED/AlternatingEdge.pdf

make a flip-flop that can alternately be positive- or negative-edge
triggered, by adding XOR in front of clock input and tying one XOR
input back to output.

BUT... DELAY switch-over to avoid racing.

My 74HC74 model indicates it can't cope with 20ns/20ns noise, so
faster logic is needed.

Timings, etc., for illustration only... squeeze to fit ;-)

...Jim Thompson

 

[D from BC]

My thoughts....

http://www.analog-innovations.com/SED/AlternatingEdge.pdf

make a flip-flop that can alternately be positive- or negative-edge
triggered, by adding XOR in front of clock input and tying one XOR
input back to output.

BUT... DELAY switch-over to avoid racing.

My 74HC74 model indicates it can't cope with 20ns/20ns noise, so
faster logic is needed.

Timings, etc., for illustration only... squeeze to fit ;-)

...Jim Thompson

Hey... that looks good.
It looks like a hairballized spin off of JFs circuit.
Still with 2 gate tp. Impressive....

One detail I'm wondering about...
You have Pre and Clr connected together for a system reset.
Shouldn't one or the other be used..Not both..


D from BC

 

[Jim Thompson]

Hey... that looks good.
It looks like a hairballized spin off of JFs circuit.
Still with 2 gate tp. Impressive....

One detail I'm wondering about...
You have Pre and Clr connected together for a system reset.
Shouldn't one or the other be used..Not both..


D from BC

Yep, Just spotted that myself ;-)

...Jim Thompson

 

[John Larkin]

My thoughts....

http://www.analog-innovations.com/SED/AlternatingEdge.pdf

make a flip-flop that can alternately be positive- or negative-edge
triggered, by adding XOR in front of clock input and tying one XOR
input back to output.

BUT... DELAY switch-over to avoid racing.

My 74HC74 model indicates it can't cope with 20ns/20ns noise, so
faster logic is needed.

Timings, etc., for illustration only... squeeze to fit ;-)

...Jim Thompson

I think you can eliminate the HC04 by using Qbar of the ff.

John

 

[John Larkin]

Yep, Just spotted that myself ;-)

...Jim Thompson

Actually, just pull them high. There's really no powerup preference
for either state.

John

 

[Jim Thompson]

I think you can eliminate the HC04 by using Qbar of the ff.

John

I don't know. BOTH the clock flip AND the D-input need delay...
otherwise SUAH timings are violated and the 74HC74 has "arrhythmia"
;-)

...Jim Thompson

 

[Jim Thompson]

Actually, just pull them high. There's really no powerup preference
for either state.

John

It's only a simulation convenience.

...Jim Thompson

 

[JosephKK]

John Larkin [email protected] posted to
sci.electronics.design:

Fred Bartoli [email protected] posted to
sci.electronics.design:

Le Sun, 04 Nov 2007 08:17:33 -0800, JosephKK a écrit:

D from BC [email protected] posted to
sci.electronics.design:

[snip]

Just do it in a modern CPLD, and 10nsec should be easy. Though
there's a bit of overhead getting started in CPLDs, it's cool
that when you make a mistake in your logic or see some
improvement, it's just a re-route.

For logic (if you are willing to get away from your SN7474 and
SN7486
parts...), you could use LVC parts at 5 volts. They're fast.

Cheers,
Tom

Thanks for the headsup for the future.

Did a quick read on
http://en.wikipedia.org/wiki/CPLD

:O .ohhhh that looks scary...

Is CPLD work more complicated than programming microcontrollers
with assembly?


D from BC

No, not really, just different.

When I was a kid I did program 6800/6809 in hexa (no assembler
available). Well one of my first tasks was writing a line editor
and an assembler, all that in hexa.

I certainly would not do that for CPLDs.

OW. That is ugly and painful just to think of.

The original Signetics PLAs were programmed by marking Xs on a form
to indicate where to blow fuses. It wasn't all that bad.

I think one could program a PAL or even a 22V10 at the fuse level
without extreme agony, although there are easier ways to do it.

John

Though i did not design it that way, i could certainly translate the
design into the fuse patterns at the time. I expect i could still do
it today. Not that i would want to.

 

[JosephKK]

John Larkin [email protected] posted to
sci.electronics.design:

Schematic?

John

I finally managed to post one.
Decided on 20 pF instead.

 

[Ken S. Tucker]

Input ------>
OR ====> o/p
----> |
|__________ |
|
cap
|
ground

Regards
Ken