Debouncing....at About 1Mhz

[D from BC]

?? That a new link form for me..How do I see?

D from BC

 

[D from BC]

---
I think this'll work, conceptually, but to get that <10ns in-out
delay (especially considering the propagation delay through the
one-shot)you'll probably need to go ECL since even FAST is iffy.

View in Courier:

___
SET
IN>-+-----------------A /
| NAND Y------A
+-[250ns]--+------B NAND Y--+-->OUT
| \ / \ +--B |
| \ / DLY1 | |
| / | A--+
| / \ DLY2 +--Y NAND
| / \ / B--+
+-[250ns]--+------A |
| OR Y------------+
+-----------------B \___
RST

The blocks labeled '250ns are cross-coupled one-shots, the top one
high-going edge triggered and the bottom one low-going edge
triggered. When either one is hot it keeps the other one from
triggering on the bounce transitions after the first edge.

Here's the timing:

_ _ _ _ ___________ _ _____ _ _ _ _
IN___|_|_|_|_| |_|_|_|_|___________

---
Oops---

_ _ _ _ ___________ _ _____ _ _ _
IN___| |_|_|_| |_|_|_|_|___________

Wow! You guys seem to be hitting rock bottom in circuit reduction.

I was going back to block diagrams that were turning into some bloated
circuits.

I did one drawing with the input waveform driving 4 circuits
simultaneously:
1 negative edge triggered one shot (ex. HC123)
1 positive edge triggered one shot
1 Negative edge ff
and 1 Positive edge ff.
Then tried some convoluted cross clearing between all of the above..
Sprinkled with gates where needed for decoding and to shorten the
in/out edge delay.

I think if I boiled down what I got... it would look something like
the above (quoted) circuit.

D from BC

 

[John Fields]

It is not.

0 xor 0 = 0

1 xor 1 = 0

---
Yup, you're right. I glossed over the delay chain and didn't notice
the grounds. But, there's an even bigger error in that the output
should be Q\ since what's on D will be old data every time clock
goes high and what you want as an output is its complement, as Tom
Bruhns noted earlier, I believe.

There's also the question of input-to-output delay, and looking at
74ACXX, the typical prop delays are, for an 86 and a 74, 4.5 and
8.0ns respectively, which doesn't quite meet the 10ns spec. Max
prop delays are 8.5 and 10ns respectively, which is almost twice the
spec.

So, it looks like that, without culling, PECL is the way to go. no?

 

[John Larkin]

---
Yup, you're right. I glossed over the delay chain and didn't notice
the grounds. But, there's an even bigger error in that the output
should be Q\ since what's on D will be old data every time clock
goes high and what you want as an output is its complement, as Tom
Bruhns noted earlier, I believe.

There's also the question of input-to-output delay, and looking at
74ACXX, the typical prop delays are, for an 86 and a 74, 4.5 and
8.0ns respectively, which doesn't quite meet the 10ns spec. Max
prop delays are 8.5 and 10ns respectively, which is almost twice the
spec.

So, it looks like that, without culling, PECL is the way to go. no?

No.

Modern cmos flipflops have Q and Qbar, so take your pick. They are
fast, too.

John

 

[John Fields]

On Fri, 02 Nov 2007 04:36:39 -0500, John Fields


No.

Modern cmos flipflops have Q and Qbar, so take your pick. They are
fast, too.

---
The point isn't that they have Q and Qbar, it's that you made a
mistake by specifying, verbally and graphically, that the output be
taken from Q.

And yes, they're fast, but not fast enough to guarantee an
input-to-output delay of <=10ns without testing the devices for
speed. That is, unless you know of a faster CMOS logic family than
FACT. Do you?

 

[D from BC]

---
Yup, you're right. I glossed over the delay chain and didn't notice
the grounds. But, there's an even bigger error in that the output
should be Q\ since what's on D will be old data every time clock
goes high and what you want as an output is its complement, as Tom
Bruhns noted earlier, I believe.

There's also the question of input-to-output delay, and looking at
74ACXX, the typical prop delays are, for an 86 and a 74, 4.5 and
8.0ns respectively, which doesn't quite meet the 10ns spec. Max
prop delays are 8.5 and 10ns respectively, which is almost twice the
spec.

So, it looks like that, without culling, PECL is the way to go. no?

Oh oh...looks like the road gets bumpy around 10nS...

I'd rather get off the logging road and steer back onto the highway
with the low speed limit.

I'd go for the best that can be done with the 74X series to start.
That <10nS time is based on 1/10th of the total of other delays in my
system. So..It can be relaxed.

I could handle up to 100nS of edge delay but the circuit loses it's
'cool' appeal.
Like driving a bicycle instead of a motorcycle.

I can probably do a ultra fast version another day.

D from BC

 

[Tom Bruhns]

Oh oh...looks like the road gets bumpy around 10nS...

I'd rather get off the logging road and steer back onto the highway
with the low speed limit.

I'd go for the best that can be done with the 74X series to start.
That <10nS time is based on 1/10th of the total of other delays in my
system. So..It can be relaxed.

I could handle up to 100nS of edge delay but the circuit loses it's
'cool' appeal.
Like driving a bicycle instead of a motorcycle.

I can probably do a ultra fast version another day.

D from BC

Just do it in a modern CPLD, and 10nsec should be easy. Though
there's a bit of overhead getting started in CPLDs, it's cool that
when you make a mistake in your logic or see some improvement, it's
just a re-route.

For logic (if you are willing to get away from your SN7474 and SN7486
parts...), you could use LVC parts at 5 volts. They're fast.

Cheers,
Tom

 

[Tom Bruhns]

---
The point isn't that they have Q and Qbar, it's that you made a
mistake by specifying, verbally and graphically, that the output be
taken from Q.

And yes, they're fast, but not fast enough to guarantee an
input-to-output delay of <=10ns without testing the devices for
speed. That is, unless you know of a faster CMOS logic family than
FACT. Do you?

Oh, good heavens. Isn't this beat to death yet??

TI 74LVC2G74: max 4.4nsec clock to /Q over temp at 5V+/-0.5V
TI 74LVC1G386: max 3.5nsec input to output, same conditions
yields max 7.9nsec over temperature. Assumes max 15pF load, which
seems reasonable under the circumstances of low fanout.

It is, of course, pretty easy to find parts to do it faster if you
really want.

Cheers,
Tom

 

[John Larkin]

What the hell is your problem? I suggested a circuit to solve a
problem, for free, and someone else, not you, pointed out that the
output is inverted. It is: So what? Use Qbar or swipe an xor section
and fix it, with my blessings. All you pointed out was that you didn't
understand the clock chain.

My ego isn't invested in this, but apparently yours is.

And yes, they're fast, but not fast enough to guarantee an
input-to-output delay of <=10ns without testing the devices for
speed. That is, unless you know of a faster CMOS logic family than
FACT. Do you?

Sure, several. FACT is decades old.

John

 

[John Larkin]

Oh oh...looks like the road gets bumpy around 10nS...

I'd rather get off the logging road and steer back onto the highway
with the low speed limit.

I'd go for the best that can be done with the 74X series to start.
That <10nS time is based on 1/10th of the total of other delays in my
system. So..It can be relaxed.

I could handle up to 100nS of edge delay but the circuit loses it's
'cool' appeal.
Like driving a bicycle instead of a motorcycle.

I can probably do a ultra fast version another day.

D from BC

If you can tolerate edge delay, just lowpass the input (rc or rlc) and
run it through a schmitt gate.

Where is this horrible signal coming from?

John

 

[John Fields]

What the hell is your problem? I suggested a circuit to solve a
problem, for free, and someone else, not you, pointed out that the
output is inverted. It is: So what? Use Qbar or swipe an xor section
and fix it, with my blessings. All you pointed out was that you didn't
understand the clock chain.

My ego isn't invested in this, but apparently yours is.

---
Really? I readily admitted that I made a mistake by glossing over
the clock chain, but you seem to be getting hot under the collar for
having been called to account for committing the same sort (one
would hope) of error regarding the direction of the output.

 

[John Larkin]

---
Really? I readily admitted that I made a mistake by glossing over
the clock chain, but you seem to be getting hot under the collar for
having been called to account for committing the same sort (one
would hope) of error regarding the direction of the output.

I'm not hot, and you can't "call me to account" because I don't answer
to you. If you want to keep your private score, go for it.

---


---
Geez, then, instead of all those cutesy pussyfooting tease tactics,
why don't you just give the OP a break and specify what you had in
mind? It is, after all, _your_ design, isn't it? Or does support
not come with it?

It's not a design, it's a suggestion. It doesn't cost anything and it
doesn't come with a warranty.

If you want logic, look at ONsemi, Fairchild, or TI. They have some.

John

 

[John Fields]

I'm not hot,

---
Then: "What the hell is your problem?" is your normal tone of voice?
---

and you can't "call me to account" because I don't answer
to you.

---
Well, of course you don't have to answer to me, but you certainly
have to account for your errors.
---

If you want to keep your private score, go for it.

---
Geez, John, thanks for your permission!
---

It's not a design, it's a suggestion. It doesn't cost anything and it
doesn't come with a warranty.

 

[Ken S. Tucker]

[snip]

Just do it in a modern CPLD, and 10nsec should be easy. Though
there's a bit of overhead getting started in CPLDs, it's cool that
when you make a mistake in your logic or see some improvement, it's
just a re-route.

For logic (if you are willing to get away from your SN7474 and SN7486
parts...), you could use LVC parts at 5 volts. They're fast.

Cheers,
Tom

Thanks for the headsup for the future.
Did a quick read onhttp://en.wikipedia.org/wiki/CPLD
:O .ohhhh that looks scary...

I like this family, claims to be 50 Mhz,
http://www.datasheetcatalog.com/datasheets_pdf/7/4/H/C/74HC175.shtml
Cheap too, otherwise I won't have a bunch of
74HCTLS175N's in stock!
Regards
Ken

 

[D from BC]

Just do it in a modern CPLD, and 10nsec should be easy. Though
there's a bit of overhead getting started in CPLDs, it's cool that
when you make a mistake in your logic or see some improvement, it's
just a re-route.

For logic (if you are willing to get away from your SN7474 and SN7486
parts...), you could use LVC parts at 5 volts. They're fast.

Cheers,
Tom

Thanks for the headsup for the future.

Did a quick read on
http://en.wikipedia.org/wiki/CPLD

:O .ohhhh that looks scary...

Is CPLD work more complicated than programming microcontrollers with
assembly?


D from BC

 

[John Larkin]

Oh, good heavens. Isn't this beat to death yet??

TI 74LVC2G74: max 4.4nsec clock to /Q over temp at 5V+/-0.5V
TI 74LVC1G386: max 3.5nsec input to output, same conditions
yields max 7.9nsec over temperature. Assumes max 15pF load, which
seems reasonable under the circumstances of low fanout.

It is, of course, pretty easy to find parts to do it faster if you
really want.

Cheers,
Tom

Somebody makes a tiny-logic cmos flipflop with Tpd of 1 ns. That's as
fast as 10KH ecl.

John

 

[D from BC]

If you can tolerate edge delay, just lowpass the input (rc or rlc) and
run it through a schmitt gate.

Where is this horrible signal coming from?

John

The signal is off a comparator that's bouncing due to some ring off an
inductor..
I'm not making any changes upstream. That's all firm and I've beaten
that part to death for the least amount of bounce..

On the matter of posts with circuit errors...
I don't mind circuits with errors...
Heck..If somebody posts a fortune cookie message, I can probably turn
it into a circuit.
"When you have square mice...Use 4 mouse traps.."
ok...I just made that up...but it's slightly relevant to the debounce
circuit I'm working on.

I often see the ideas, paths,get the gist or objectives of circuits
even if a circuit doesn't work..
When I get circuit ideas it's kinda like a dart board full of darts.
One can roughly determine where the target is by all the positions of
the darts.

D from BC

 

[John Larkin]

I think I spotted that part while browsing ff's on Digikey.
IIRC that part is so small..fleas can use it as a coffee table.

D from BC

Yup, NC7SV74. But you can get it in the bigger US8 package, which you
can practically see with your naked eye. In bright light.

Some of these TinyLogic parts can put almost 5 volts into 50 ohms with
a risetime of 600 ps or so.

John

 

[John Larkin]

The signal is off a comparator that's bouncing due to some ring off an
inductor..
I'm not making any changes upstream. That's all firm and I've beaten
that part to death for the least amount of bounce..

On the matter of posts with circuit errors...
I don't mind circuits with errors...

I don't mind if somebody points out an error, or better yet suggests
an improvement, or riffs on an idea. This is just play. Some people
play whack-a-mole with ideas, pounding them as soon as they pop up.

Heck..If somebody posts a fortune cookie message, I can probably turn
it into a circuit.

When we bought our building, it was a working fortune-cookie factory,
owned by the Louie family.

http://s2.supload.com/free/FortCookMach.JPG/view/

They gave us a couple of big boxes of cookies with the building, and
here were the first two I opened:

http://s2.supload.com/free/Fortunes.jpg/view/

Google "Louie Fortune Cookie Machine" for some history.

John

 

[D from BC]

Somebody makes a tiny-logic cmos flipflop with Tpd of 1 ns. That's as
fast as 10KH ecl.

John

I think I spotted that part while browsing ff's on Digikey.
IIRC that part is so small..fleas can use it as a coffee table.

D from BC