Core losses in dual big inductors

[Joerg]

PSpice actually models cores. But I've never exorcized one >:-}

Modeling is fairly useless if you can't get the data for it. What is
output is no better than what you can input ...

 

[Joerg]

Indeed! Simulations are only as accurate as the models.

For an amusing exercise, peruse and ponder LTspice's "alternate"
solver and what different "parsing" means >:-}

You'll be stunned when you realize what's going on.

It'll run a lot slower. I don't see how that would elucidate much on the
topic of core loss if once cannot get enough hard data about the ferrite
behavior.

 

[Joerg]

Jim Thompson wrote:

[...]

It'll run a lot slower. I don't see how that would elucidate much on the
topic of core loss if once cannot get enough hard data about the ferrite
behavior.

The "normal" solver executable "parses" the schematic and loads ALL
MODELS as BEHAVIORAL so as to attain bragging rights for best speed
over all other simulators.

When this approach hangs, or gives fallacious results, you use the
"alternate" solver which "parses" the schematic and loads real Spice
models... e.g. diodes are no longer modeled as ideal switches, the
real diode model is loaded ;-)

Huh? I am runnning LTSpice sims right now for a HV converter. Actually
since tonight. No sleep, the root under a big crown has gone off :-(

The diodes are never assumed as ideal switches, including the one in the
standard LTSpice library. What is behavioral is their chips. But without
that a switcher start-up sim would take forever.

Too much bragging is made about speed... haste makes waste.

It seems what is needed is a Spice model of cores that properly models
core loss during a transient simulation... the AC model doesn't do it.

As I mentioned before, PSpice has Jiles-Atherton core models. I've
not played with these so I know not if that models core losses, but
I'm going to look into it. And perhaps write my own behavioral
equivalent which will play under other Spice Variants.

AFAIK Jiles-Atherton takes hysteresis, saturation and all that into
account but not core losses. But it would be needed in the calculations.
Is the other one the Preisach model?

Likewise encrypted models... peeves me seriously. So I'm going to run
them under their native simulator and write a general-use behavioral
version right beside it and match all parameters. And distribute
freely >:-}

That peeves me as well. Unfortunately all chip mfgs do it. And then
everyone and their brother wants you to use their proprietary simulator.
For LTC this has worked, I have used their chips on pretty much all
design where cost was not a high priority. Like the one I am working on
right now, all four converters are LTC-equipped. Due to LTSpice that
lowers the design risk substantially.

 

[Tim Williams]

Which is why I explicitly rejected putting the winding on the same
board as the rest of the circuit.

Needs two boards, but occupies the space better -- should be easy to make
one in a 4mm height. Footprint is still probably too big though. Maybe
some chip Rs and Cs can be placed under it still?

The fill factor for round copper wires isn't 100% - closer to 70%
IIRR - and some board manufacturers can put down copper layers that are
thicker than than board material, so you can probably get pretty close
to round wire copper fill factors, and - in theory - might even be able
to do a bit better. But it would take a specialist printed circuit
board manufacturer to get you there.

I typically guess 50% ff on my transformers, mainly for bobbin and tape
and not-quite-full layers, but also just because.

I don't think PCBs can go over 30%, at least very usefully. (Yeah you can
make a trace 500 mil wide, but how much of that is actually carrying
current?) I asked one well-established manufacturer, and they said you
can't go with thinner traces than the thickness (obviously, no 10 mil
traces on a 20 mil 'heavy copper' layer), and the prepreg inbetween
likewise has to be thicker than the copper (some has to squeeze inbetween
the traces of the facing layer, I suppose). A typical winding for
something like this might use, oh, 2 or 4oz copper, 40 mil width traces,
8-10 mil spacing, and 10 mil prepreg (possibly 5 or 7.5 mil, you'd have to
check). Enough layers for the required amp turns, and as many turns as
can be squeezed in there.

Copper foil windings (foil in the winding plane, rather than printed)
might be useful, but eddy currents chew them up, especially the inner
turns of an inductor. Some companies claim to have a litz patterned foil
that avoids that, don't know if they make anything microscopic enough for
a mere 10 amps though (it's more of a 50A+ thing).

Tim

 

[Tim Williams]

Not really. There is a lot of hand-waving, inaccurate information,
missing data. With inductors it usually already ends at the telephone,
at the point where you ask which core material they use. Almost like
asking Coca Cola about the secret sauces and magic potions in their
concentrate.

That secrecy is the reason why I never really looked into simulation
software for core loss. If you don't know where they get the cores it
wouldn't make much sense.

I've ran across a few series that actually provided core loss info. Not
the most useful parameters (in terms of Bmax, yes, I know exactly what
that is...sure..), but at least it's a start. They are by far the
minority, which is bizarre, as if they never expected that us designers
would, you know, actually apply AC to them, you know, use inductors to
induct!

I did once contact Bourns regarding one of their toroidial parts, which
they stated uses a particular Kool-Mu core. That was handy.

From another occasion, those Murata pulse transformers use Ferroxcube 3F3
cores, not too shabby.

Tim

 

[Joerg]

Lots of references...

http://www.psma.com/coreloss/supplement.pdf

http://fmtt.com/Transformer SPICE Model 2-14-08.pdf

http://www.edacafe.com/books/PSpice/san63267_ch02.pdf

http://www4.ee.bgu.ac.il/~pel/pdf-files/jour112.pdf

Now to see if I can make sense of this academic hand waving >:-}

In real life it's going to be complicated. There are unmentioned air
gaps (epoxy that is often ferrite-colored), Eddy currents that will
depend on core shapes, and so on. I think there has to be some sort of
behavioral set as well, that gets experimentally evaluated for each core
shape and size. Possibly even for each inductor.

Anyhow, in our case we'll have to measure it. So far we are down to
about 50C above ambient. Mucho mejor que 85 grados. That is still a good
10 degrees more than I like but I think we'll get there.

 

[Joerg]

I've ran across a few series that actually provided core loss info. Not
the most useful parameters (in terms of Bmax, yes, I know exactly what
that is...sure..), but at least it's a start. They are by far the
minority, which is bizarre, as if they never expected that us designers
would, you know, actually apply AC to them, you know, use inductors to
induct!

I did once contact Bourns regarding one of their toroidial parts, which
they stated uses a particular Kool-Mu core. That was handy.

From another occasion, those Murata pulse transformers use Ferroxcube 3F3
cores, not too shabby.

We are now trying to find the sweet spot between winding loss and core
loss, where there is sort of an equilibrium. But first there will be an
emergency session at my dentist. A root under a large crown has gone
off. Wish me (and my wallet ...) luck.

 

[Fred Abse]

As I mentioned before, PSpice has Jiles-Atherton core models. I've not
played with these so I know not if that models core losses, but I'm going
to look into it. And perhaps write my own behavioral equivalent which
will play under other Spice Variants.

It might be interesting to compare the same core using Jiles-Atherton, and
The Chan model that LTspice has.

 

[DecadentLinuxUserNumeroUno]

The "normal" solver executable "parses" the schematic and loads ALL
MODELS as BEHAVIORAL so as to attain bragging rights for best speed
over all other simulators.

When this approach hangs, or gives fallacious results, you use the
"alternate" solver which "parses" the schematic and loads real Spice
models... e.g. diodes are no longer modeled as ideal switches, the
real diode model is loaded ;-)

Too much bragging is made about speed... haste makes waste.

It seems what is needed is a Spice model of cores that properly models
core loss during a transient simulation... the AC model doesn't do it.

As I mentioned before, PSpice has Jiles-Atherton core models. I've
not played with these so I know not if that models core losses, but
I'm going to look into it. And perhaps write my own behavioral
equivalent which will play under other Spice Variants.

Likewise encrypted models... peeves me seriously. So I'm going to run
them under their native simulator and write a general-use behavioral
version right beside it and match all parameters. And distribute
freely >:-}

...Jim Thompson

They also need to handle more complex transformers. Like any that
would include say, a feedback winding.

And gapped cores/core gapping, which alters the entire tableau.

 

[Fred Abse]

Does anyone actually specify core loss? Or a Spice model that actually
works in transient analysis? All I find model AC (small signal) lossiness
only.

Epcos do. I've had good results with Epcos cores, using their "Ferrite
Magnetics Design Tool", then translating their hysteresis curves into the
Chan model, and their loss figures into lumped resistance in parallel.
Gets pretty near actual measurements. Works in .tran, no problem.

 

[Joerg]

I gave up licorice taffy last year after I encountered a strange hard
spot in my taffy... $400 :-(

Oops. Just came back, the bill will be painful but not written yet.
Because they took me in as an emergency and didn't fire up the server.
1h+ session, the dentist gave me the legal limit for anesthetics, not
enough, had to go in anyhow, what else can ya do ... ouch, ouch. But now
it's done.

Best dentist we ever had. But he is well into his 70's and when he ever
retires I don't know what we are going to do.

 

[Joerg]

The best way to design a switcher seem to be: simulate to get the
basic dynamics close, then buy a bunch of parts and breadboard.
Extensive simulation probably isn't justified, because the part models
(magnetics, fets, cap ESR, thermals, all that) aren't worth the effort
to get accurate. And you get to get out of your chair and drill and
solder and stuff.

Mine usually go directly from simulator to CAD and then to fab. So we
get complete proto boards back. On simple designs that's usually it,
goes into production like that after testing.

I found that the simulations are darn close to the real-life results
later, except you never quite know how hot the core will get. This time
it was a bit much but it was a complicated design.

 

[Klaus Kragelund]

I'm pondering that it may be possible to make a subcircuit that will

come quite close... without having any complex core model available.



We know that the losses are proportional to the flux change and to the

frequency to some power. So maybe a few measurements on a core to get

the coefficients, then create a subcircuit that has an extra pin that

shows power dissipated. (We'd still have the thermal resistance issue

to ponder.)



Most of the switchers I've made are really high power, like 5V/400A,

with fist-sized Ferroxcube E-E transformers, or very small... like

12V/20mA for cellphone touch screens.



Cool, in all cases... as I've told about the "cool" one that had 400V

P-P on the mounting flag ;-)

As for the simulation of magnetics in PSpice, the magnetics simulation toolallows for advanced simulation of Magnetics and Ferroxcube parts (other third party manufactors can be added) including detailed information on bobbin and even insulation materials. It even has a wizard when creating the model the will check against fill factor and guide through the construction ofthe part if needed.

Cheers

Klaus

 

[[email protected]]

I can't keep engineering boards around. Somebody always ships them as
demos, or sells them. I should disfigure them.

At a past job, there were a couple of boards that had mods that were
unobvious to the naked eye but that made them Different than production.
I wrote "Engineering" on the RF shield cans in Sharpie. I may have also
written it on the board, too... I wouldn't put it past one manager to
swap graffiti-free shield cans onto the board so he could ship it. This
board was the size of one of your VME boards, though, and had several
1.5" x 2" or so shield cans. Harder to do on a tiny board.

I threatened to paint the front panels pink, but I never got brave
enough to. One of my co-workers liked to run engineering boards without
a front panel if he could get away with it.

I have heard of, but not personally seen, somebody soldering a few
"mistake" wires onto a board... they went from +5 V to +5 V or ground to
ground, but they were allegedly enough to stop the boards from being
shipped.

Matt Roberds

 

[legg]

Does anyone actually specify core loss? Or a Spice model that
actually works in transient analysis? All I find model AC (small
signal) lossiness only.

...Jim Thompson

A lot of the early bobbin cores for SMD were/are pressed iron dust,
that really weren't meant for large deltaB. This is usually the reason
why loss isn't specified. The shapes aren't cheaply obtainable in
ferrite.

If the material is recognizable, then yes, core loss is a standard
specification.

I'm not a fan of some of the representations made for core loss
calculation formulas, but Siemens/Epcos, Philips/Ferroxcube and
MagneticsInc are pretty good at coming up with coefficients that
correspond to the earlier work of Snelling for ferrites. This is the
most common material used in serious HF magnetics experiencing larger
AC flux excursions.

Magnetics has tried to extend this to some of the higher flux, lower
permeability powder cores, but has yet to present proper
ferrite/powder correlation.

A search for "Magnetics-Ferrite-Core-Loss-Equations" will find a
spreadsheet that might be of interest.

RL

 

[Fred Abse]

Though some have said there's a "Chan" model in LTspice. Is Joerg
overlooking a built-in solution for those who adhere to "free" ?

Quick and dirty simulation to plot B-H loop of EP7 core in H5A ferrite.
Ungapped, alter parameter LG for required gap (in meters):

Use the plot file (at end) to set plot to read directly in amp/meter and tesla.

Version 4
SHEET 1 1008 680
WIRE 192 80 -32 80
WIRE 448 80 304 80
WIRE 512 80 448 80
WIRE 304 96 304 80
WIRE 448 96 448 80
WIRE -32 128 -32 80
WIRE 192 128 192 80
WIRE -32 256 -32 208
WIRE 80 256 -32 256
WIRE 192 256 192 208
WIRE 192 256 80 256
WIRE 80 288 80 256
FLAG 80 288 0
FLAG 512 80 OUT
IOPIN 512 80 Out
FLAG 304 176 0
FLAG 448 176 0
SYMBOL ind 176 112 R0
WINDOW 3 29 104 Left 2
SYMATTR Value Hc=8 Br=100e-3 Bs=410e-3 Lm=15.7e-3 Lg=0 A=10.3e-6 N=10
SYMATTR InstName L1
SYMBOL bv 304 80 R0
SYMATTR InstName B1
SYMATTR Value V=idt(v(n001))
SYMBOL current -32 208 R180
WINDOW 0 24 80 Left 2
WINDOW 3 -106 36 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value SINE(0 .5 1000)
SYMBOL res 432 80 R0
SYMATTR InstName RB1
SYMATTR Value 1meg
TEXT -40 296 Left 2 !.tran 0 2m 0 100n


Plot File:

[Transient Analysis]
{
Npanes: 1
{
traces: 1 {524290,0,"V(out)/(10*10.3e-6)"}
Parametric: "I(L1)*10/15.7e-3"
X: (' ',0,-420,70,420)
Y[0]: ('m',0,-0.4,0.08,0.4)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: ('m',0,0,0,-0.4,0.08,0.4)
Log: 0 0 0
GridStyle: 1
}
}

 

[Bill Sloman]

I know. I was just pondering how to make a more universal tool.

Though some have said there's a "Chan" model in LTspice. Is Joerg
overlooking a built-in solution for those who adhere to "free" ?

The "Chan" model in LTSpice only works for isolated inductors - you can't directly couple such an inductor to other inductors to simulate a transformer.

 

[Tim Williams]

Is this the Tim Williams that has posted here...

http://www.seventransistorlabs.com/IndLoss/Core_Loss.pdf

It is, but that only helps once you know the losses.

I suppose one could go backwards once a particular inductor has been
tested (how many watts is 50C temp rise?), assuming AC+DC copper losses
can be teased apart. Destructive testing of a part would be informative
with regards to winding construction (wire diameter, turns spacing,
layers; skin depth, proximity effect; AC/DC resistance ratio), and would
also tell number of turns and core area.

Tim

 

[Fred Abse]

Thanks, Fred!

Am I correct in assuming, no loop, no losses?

Does saturation have a loss mechanism?

Yes. I've got something similar, that does hysteresis loss. I'll dig it
out and post it.

 

[boB]

Though some have said there's a "Chan" model in LTspice. Is Joerg
overlooking a built-in solution for those who adhere to "free" ?

Quick and dirty simulation to plot B-H loop of EP7 core in H5A ferrite.
Ungapped, alter parameter LG for required gap (in meters):

Use the plot file (at end) to set plot to read directly in amp/meter and tesla.

Version 4
SHEET 1 1008 680
WIRE 192 80 -32 80
WIRE 448 80 304 80
WIRE 512 80 448 80
WIRE 304 96 304 80
WIRE 448 96 448 80
WIRE -32 128 -32 80
WIRE 192 128 192 80
WIRE -32 256 -32 208
WIRE 80 256 -32 256
WIRE 192 256 192 208
WIRE 192 256 80 256
WIRE 80 288 80 256
FLAG 80 288 0
FLAG 512 80 OUT
IOPIN 512 80 Out
FLAG 304 176 0
FLAG 448 176 0
SYMBOL ind 176 112 R0
WINDOW 3 29 104 Left 2
SYMATTR Value Hc=8 Br=100e-3 Bs=410e-3 Lm=15.7e-3 Lg=0 A=10.3e-6 N=10
SYMATTR InstName L1
SYMBOL bv 304 80 R0
SYMATTR InstName B1
SYMATTR Value V=idt(v(n001))
SYMBOL current -32 208 R180
WINDOW 0 24 80 Left 2
WINDOW 3 -106 36 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value SINE(0 .5 1000)
SYMBOL res 432 80 R0
SYMATTR InstName RB1
SYMATTR Value 1meg
TEXT -40 296 Left 2 !.tran 0 2m 0 100n


Plot File:

[Transient Analysis]
{
Npanes: 1
{
traces: 1 {524290,0,"V(out)/(10*10.3e-6)"}
Parametric: "I(L1)*10/15.7e-3"
X: (' ',0,-420,70,420)
Y[0]: ('m',0,-0.4,0.08,0.4)
Y[1]: ('_',0,1e+308,0,-1e+308)
Volts: ('m',0,0,0,-0.4,0.08,0.4)
Log: 0 0 0
GridStyle: 1
}
}

Thanks, Fred!

Am I correct in assuming, no loop, no losses?

Does saturation have a loss mechanism?

I find that I can lose semiconductors when magnetics saturate !

boB