clocks of ic-74LS95

[bhuvanesh]

Here two clocks are used CP2 for loading parallel data's and CP1 for loading data serially by shifting .Why two clocks are being used here.Thank you in advance.

 

[KrisBlueNZ]

You've answered your own question. The two clocks are needed because they do different things.

The 74xx95 shift register can operate in two different modes, as selected by the S pin (pin 6). If S is high, a falling edge (high to low transition) on CP2 causes the data on the four parallel inputs (pins 2, 3, 4 and 5) to be transferred into the 4-bit shift register. If S is low, a falling edge on CP1 causes the data in the shift register to shift along by one bit.

The outputs of all stages of the shift register are available on pins 10~13. The last stage output is on pin 10. This is the pin you would use when converting parallel data to serial.

The 74xx95 appears to be obsolete. Why are you studying it?

Edit: If you're asking why there are two separate clock pins when only one clock can ever be active at a time, I guess it's for convenience. The designer will usually have those two clocks on separate signals in his/her circuit, and if there was only one clock input on that IC, the two sources would have to be multiplexed onto it, according to the state of the S signal.

 

[bhuvanesh]

1)

The 74xx95 appears to be obsolete. Why are you studying it?

i believe great things can be learnt from obsolete things.i am reading Digital circuits by morris mano.The example ic give there is ,this.
2)
Thats my question why do we want to have two clocks un neccessarily if one can satisfy our needs
example one clock (40MHz) can be used for parallel transfer when S i HIGH that it load all data at one clock pulse ,the same one is used for serial when S is LOW that loads one bit of data at every clock pulse.
3)
Here the clock is gated .so that will cause some propagation delay that lead error in clock period ,right?
Thank you

 

[KrisBlueNZ]

Thats my question why do we want to have two clocks un neccessarily if one can satisfy our needs

As I said, convenience for the circuit designer.

example one clock (40MHz) can be used for parallel transfer when S i HIGH that it load all data at one clock pulse ,the same one is used for serial when S is LOW that loads one bit of data at every clock pulse.

Yes, they could have done it that way. And they might have, if they didn't have enough pins.

Here the clock is gated .so that will cause some propagation delay that lead error in clock period ,right?

Yes, a tiny bit.

 

[bhuvanesh]

okay one more thing,kind of personel what you get of answering me any points ,money.
sorry if i asked anything wrong about

 

[KrisBlueNZ]

Just the satisfaction of helping a fellow human being solve their problem

"... for the children."
-- Lawrence Jamieson, Dirty Rotten Scoundrels

 

[bhuvanesh]

Thank you for that