Can anyone identify the manufacturer of this Chip ?

[Jan Panteltje]

WTF ?!

_cheap_ things do not have to be shit, or am I mistaken here?

the 8*SPI in parallel is hardly more expensive in hardware terms then
proper design.

besides the SPI parallel trick need read sync as even same card will
not respond with same clock cycle delay to read commands, so the clock
lines need separate steering. It way more reasonable to make device
that runs 2 SD card in parallel (in 4 bit mode)

Antti

From:
http://en.wikipedia.org/wiki/Secure_Digital_card
------------------------------------------------------------
Technical explanation

SD supports at least three transfer modes:

* One-bit SD mode (separate command and data channels and a proprietary transfer format)
* Four-bit SD mode (uses extra pins plus some reassigned pins)
* SPI mode (basically, a simpler subset of the SD protocol for use with microcontrollers)

All memory cards must support all three modes, except for microSD where SPI
is optional. The cards must also support clock frequencies of up to 25 MHz
for regular cards, and 50 MHz for high-speed cards.

Royalties for SD/SDIO licenses are imposed for manufacture and sale of
memory cards and host adapters ($1000 per year plus membership at
$1500/year) but SDIO cards can be made without royalties and MMC host
adapters do not require a royalty.
-------------------------------------------------------------

So, I dunno. SD 2500$ /year for an adapter, how many cards will you sell? 10?
Do I see this right?
8 SD or MMC cards of 1GB is now about 64 Euro I think.
10 Euro for the rest of the parts.
250 for the license??????? Not counting other IP you will need.

You tell me.

I think if cards from the same batch are used the timing issue is not that different.
But you are right, you'd need to monitor for CRC or whatever, and wait for all 8 cards
to complete.
But the same issue applies for any other system, even or even more so if you want
to 'stagger' the cards as in this example, maybe that is why so much logic?
Maybe the guy who designed that board ran into this.

 

[Antti]

From:
http://en.wikipedia.org/wiki/Secure_Digital_card
------------------------------------------------------------
Technical explanation

SD supports at least three transfer modes:

* One-bit SD mode (separate command and data channels and a proprietary transfer format)
* Four-bit SD mode (uses extra pins plus some reassigned pins)
* SPI mode (basically, a simpler subset of the SD protocol for use with microcontrollers)

All memory cards must support all three modes, except for microSD where SPI
is optional. The cards must also support clock frequencies of up to 25 MHz
for regular cards, and 50 MHz for high-speed cards.

Royalties for SD/SDIO licenses are imposed for manufacture and sale of
memory cards and host adapters ($1000 per year plus membership at
$1500/year) but SDIO cards can be made without royalties and MMC host
adapters do not require a royalty.
-------------------------------------------------------------

So, I dunno. SD 2500$ /year for an adapter, how many cards will you sell? 10?
Do I see this right?
8 SD or MMC cards of 1GB is now about 64 Euro I think.
10 Euro for the rest of the parts.
250 for the license??????? Not counting other IP you will need.

You tell me.

I think if cards from the same batch are used the timing issue is not that different.
But you are right, you'd need to monitor for CRC or whatever, and wait for all 8 cards
to complete.
But the same issue applies for any other system, even or even more so if you want
to 'stagger' the cards as in this example, maybe that is why so much logic?
Maybe the guy who designed that board ran into this.- Zitierten Text ausblenden -

- Zitierten Text anzeigen -

the read delay is can be way different as it depends on the amount and
location of bad blonks in the NAND, this is all transparent to the
user, but the black management is done by the SD cards, what can cause
essential difference in response times.

Antti

 

[Jan Panteltje]

the read delay is can be way different as it depends on the amount and
location of bad blonks in the NAND, this is all transparent to the
user, but the black management is done by the SD cards, what can cause
essential difference in response times.

Antti

OK, I have been thinking a bit, and it seems to me we are not going to see many of
these cards on the market.
It is simpler for a manufacturer to just solder some FLASH chips on a board, it
is more reliable (no connectors), no expensive protocol (both financial and as overhead),
FLASH is still falling in price (some 'up' predicted for next year perhaps).
Maybe the FLASH chips are even cheaper then the SDcard connectors ;-)
You'd have to do bad sector handling on board, but so what.
Let's forget about this product

 

[Antti]

OK, I have been thinking a bit, and it seems to me we are not going to see many of
these cards on the market.
It is simpler for a manufacturer to just solder some FLASH chips on a board, it
is more reliable (no connectors), no expensive protocol (both financial and as overhead),
FLASH is still falling in price (some 'up' predicted for next year perhaps).
Maybe the FLASH chips are even cheaper then the SDcard connectors ;-)
You'd have to do bad sector handling on board, but so what.
Let's forget about this product

you can forget
eh well I am doing several projects that are using SD Cards, so I keep
my mind open

as of nand Flash there are NAND flash with built in ATA
and there are NAND flash with built in SD card interface
and there are NAND flash with built in USB interface
and NAND flash with "differential clock" for high speed

....

so lots of thinking, what makes sense and where..

Antti

 

[Antti]

sure, its very simple:

[ATA device IP Core] < BUFFER > [SD Host IP Core]
+ some small management state machine.

You assume that the operation of the buffers is trivial. I suspect it
may not be. Even the ATA interface is non-trivial if you want to
support the faster transfer modes. There's probably a reason why it's
an FPGA and not simply a CPLD.

I'm sure someone could make a more cost-optomized design, but at the
extremes of that, performance may suffer. Of course we could also be
looking at a product where someone plunked down the parts they thought
would be required to make a good solution, but shipped it before
getting their HDL code beyond minimal low-rate functionality.

it really is simple as that, but I would not call it "buffer memory of
some sort"

Oh, and absent information as to what type of "buffer memory" it is,
what exactly would you call it?

i try to assume nothing.
but, "buffer memory" would I think be proper for gadget where most of
the complexity is "memory and/or buffer"

a ATA-SD interface is something that includes some buffer memory, but
the buffer memory is not the main function, as most of complecity is
in the interface parts.

Antti

 

[[email protected]]

a ATA-SD interface is something that includes some buffer memory, but
the buffer memory is not the main function, as most of complecity is
in the interface parts.

But buffer memory, and proper handling of it, may well make all the
difference between a very good product, and a barely useable one.

There's a bunch of these chips on the board. I suspect they are
buffer memories, one per SD card. And I suspect that they are
important, or at least would be if the product ended up working the
way it was intended to when the PCBs were made, otherwise they
wouldn't be there.

There's also a controller, most likely in that spartan FPGA.
Depending on what the buffers are used to accomplish, the controlling
logic may be non-trivial.

 

[Antti]

But buffer memory, and proper handling of it, may well make all the
difference between a very good product, and a barely useable one.

There's a bunch of these chips on the board. I suspect they are
buffer memories, one per SD card. And I suspect that they are
important, or at least would be if the product ended up working the
way it was intended to when the PCBs were made, otherwise they
wouldn't be there.

There's also a controller, most likely in that spartan FPGA.
Depending on what the buffers are used to accomplish, the controlling
logic may be non-trivial.

there are 4 times IDE-SD ASIC's, from company called c-guys
1 per SD card. those chips include FULL IDE2SD interface,
each of them has local onchip buffers for 2 sector
FPGA does some management only, to combine the 4 IDE into one,
the SD IP core is not inside the FPGA at all..

Antti

 

[Andy Peters]

Agreed, was my idea too.

I've done it ...

-a

 

[Andy Peters]

I've done it ...

-a

(replying to myself ... sheesh) .. actually, not with SD cards ... but
with the NAND flash chips themselves.

-a

 

[Andy Peters]

Mark,

it depends on your definition of CPLD, if you mean CPLD as Complex
PLD, not FPGA then, well it may be still doable, but very unreasonable
as the price of CPLDs increases very quickly above 64MC.

I think Mark means that he can do whatever's necessary in some kind of
programmable logic device. Whether it's a CPLD or an FPGA is really
just a detail.

-a

 

[[email protected]]

there are 4 times IDE-SD ASIC's, from company called c-guys

So why didn't you just say that in your first post and save all this
running around in circles?

 

[Mark McDougall]

You assume that the operation of the buffers is trivial. I suspect it
may not be. Even the ATA interface is non-trivial if you want to
support the faster transfer modes. There's probably a reason why it's
an FPGA and not simply a CPLD.

Actually, if you're talking about UDMA, implementation _is_ trivial.

And for the record, I was probably a little flippant in my remark about
CPLDs... I'll defer to Antti's judgement on that one...

Regards,

 

[[email protected]]

there are 4 times IDE-SD ASIC's, from company called c-guys
1 per SD card. those chips include FULL IDE2SD interface,
each of them has local onchip buffers for 2 sector
FPGA does some management only, to combine the 4 IDE into one,
the SD IP core is not inside the FPGA at all..

The SD core may not be in the FPGA, but if the device stripes data
across the cards, which thanks to these ASICS present IDE interfaces,
wouldn't it need to implement a fully IDE target to talk to the PC,
and then multiple IDE hosts to talk to the ASICs? And quite possible
a small amount of buffering in between... beginning to make sense for
it to be an FPGA. Though perhaps not an elegant design.

Curious what that wide package device (1x) is. It looks like a flash
memory device...

 

[Mark McDougall]

there are 4 times IDE-SD ASIC's, from company called c-guys
1 per SD card. those chips include FULL IDE2SD interface,
each of them has local onchip buffers for 2 sector
FPGA does some management only, to combine the 4 IDE into one,
the SD IP core is not inside the FPGA at all..

Not a very smart design then...

 

[Imti]

Hi

Iam a newbie in linux. How to findout on an arm board that it has a
debug port to use KGDB. I have an XSCALE(IQ80310) based board and want
to use KGDB to debug my kernel module. I would like to know how to
conclude that a development board has debugging supporting hardware.

Thanks in advance....

Regards
Imtiaz Ahmed