Can anyone identify the manufacturer of this Chip ?

[RR]

I am interested in finding the manufacturer of U3 on this SSD device:
http://www.engadget.com/2007/02/19/the-do-it-yourself-ssd-adapter/

The device in question is on the underside of the PCB above the
letters "25SD".
It has a strange Logo that I do not recognize.

See : http://akiba.ascii24.com/akiba/news/2006/11/16/imageview/images825461.jpg.html

Regards,
Richard.

 

[John_H]

Couldn't start to identify the part with that image. Maybe it looks good on
your monitor but I don't care to adjust my monitor settings and get the loop
out to try and SEE the logo on that chip in the first place. Might I
suggest a better macro lens?

 

[Winfield Hill]

Couldn't start to identify the part with that image. Maybe it looks
good on your monitor but I don't care to adjust my monitor settings
and get the loop out to try and SEE the logo on that chip in the
first place. Might I suggest a better macro lens?

Richard wrote

I had trouble making it out as well. Looks fuzzily-familiar to a
Cypress logo. If you tell us the part number we can pin it down.

 

[larwe]

Couldn't start to identify the part with that image. Maybe it looks good on

I don't think the OP actually owns one, that looks like a stock/
catalog photo. And the second photo appears to be a woman's hand,
which while not incompossible with the name "Richard" is at least
unusual.

 

[Mark McDougall]

I am interested in finding the manufacturer of U3 on this SSD device:
http://www.engadget.com/2007/02/19/the-do-it-yourself-ssd-adapter/

Q. Why do you want to know?

Looking at the PCB vs the functionality, I'm having trouble understanding
why you'd need half the crap on there just to interface 4 SD cards to
IDE... and looking at the asking price it would appear that the marketing
division have as little clue as the engineering division...

Regards,

 

[Gene S. Berkowitz]

Q. Why do you want to know?

Looking at the PCB vs the functionality, I'm having trouble understanding
why you'd need half the crap on there just to interface 4 SD cards to
IDE... and looking at the asking price it would appear that the marketing
division have as little clue as the engineering division...

According to the manufacturer (Century Corp, Japan), it stripes the data
across the multiple cards to speed up access (you must install cards in
pairs).

--Gene

 

[Mark McDougall]

According to the manufacturer (Century Corp, Japan), it stripes the data
across the multiple cards to speed up access (you must install cards in
pairs).

My statement stands. You can do all that in a single CPLD...

Regards,

 

[Antti]

My statement stands. You can do all that in a single CPLD...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark,

it depends on your definition of CPLD, if you mean CPLD as Complex
PLD, not FPGA then, well it may be still doable, but very unreasonable
as the price of CPLDs increases very quickly above 64MC. If you say
that an FULL ATA compliant high speed multi SD in parallel optimized
interface can be done "cost effectivly" in simple CPLD, then this is
something that I would say is not so. OR if you are able to implement
it, then I should maybe buy an hat. (so that I can take it off, should
I meet you).

the PCB as on picture sure is using an overkill of components, but
replacing them with and small CPLD is also not possible. However an
3USD FPGA maybe already be able todo the task.


Antti

 

[Jan Panteltje]

My statement stands. You can do all that in a single CPLD...

Regards,

Agreed, was my idea too.

 

[Antti]

Agreed, was my idea too.

its of course nice idea
if the functionality could be easily implemented in small simple PLD,
then this CPLD could be sold as competing product to:

http://www.zentek.co.jp/product_sd_cg200.htm

or?

I personally would instantly buy this IP (IDE-SD interface that can
fit into CPLD), but it is a little more than "simple PLD" to achive
this, so I dont expect this to be available.

Antti

PS, hm just recalled, I have made a MMC (MMC mode, not SPI) mode IP
core that can configure FPGA from MMC card, this IP core does take 21
Macrocells (coolrunner-2), other technologies 22 MC. So I think I know
what function takes what resources in CPLD/FPGA. A high performance
standard compliant IDE-SD interface is not fittable into CPLD
(standard CPLD, not counting the cross-over products like machXO/MAX-
II to CPLD's)

 

[Jan Panteltje]

its of course nice idea
if the functionality could be easily implemented in small simple PLD,
then this CPLD could be sold as competing product to:

http://www.zentek.co.jp/product_sd_cg200.htm

or?

I personally would instantly buy this IP (IDE-SD interface that can
fit into CPLD), but it is a little more than "simple PLD" to achive
this, so I dont expect this to be available.

Antti

PS, hm just recalled, I have made a MMC (MMC mode, not SPI) mode IP
core that can configure FPGA from MMC card, this IP core does take 21
Macrocells (coolrunner-2), other technologies 22 MC. So I think I know
what function takes what resources in CPLD/FPGA. A high performance
standard compliant IDE-SD interface is not fittable into CPLD
(standard CPLD, not counting the cross-over products like machXO/MAX-
II to CPLD's)

OK, FPGA, actually I was thinking that first.
But make no mistake: what part is [in] the 'driver' and what part is the
CPLD [FPGA].
Maybe with some clever doing you could make the hardware part very simple.

 

[Antti]

its of course nice idea
if the functionality could be easily implemented in small simple PLD,
then this CPLD could be sold as competing product to:


I personally would instantly buy this IP (IDE-SD interface that can
fit into CPLD), but it is a little more than "simple PLD" to achive
this, so I dont expect this to be available.

PS, hm just recalled, I have made a MMC (MMC mode, not SPI) mode IP
core that can configure FPGA from MMC card, this IP core does take 21
Macrocells (coolrunner-2), other technologies 22 MC. So I think I know
what function takes what resources in CPLD/FPGA. A high performance
standard compliant IDE-SD interface is not fittable into CPLD
(standard CPLD, not counting the cross-over products like machXO/MAX-
II to CPLD's)

OK, FPGA, actually I was thinking that first.
But make no mistake: what part is [in] the 'driver' and what part is the
CPLD [FPGA].
Maybe with some clever doing you could make the hardware part very simple.- Hide quoted text -

- Show quoted text -

eh, if you read my replies, then I did not outrule this to be
implementatble in "3 USD FPGA",
there are not so many FPGA with <= 3 USD price tag. And yes fitting
into to cheapest FPGA
would require near-magical engineering, but could be doable.

Antti

 

[[email protected]]

My statement stands. You can do all that in a single CPLD...

It looks to me like the one-per-card chips are probably buffer
memories of some sort.

 

[Antti]

It looks to me like the one-per-card chips are probably buffer
memories of some sort.

sure, its very simple:

[ATA device IP Core] < BUFFER > [SD Host IP Core]
+ some small management state machine.

it really is simple as that, but I would not call it "buffer memory of
some sort"

Antti

 

[[email protected]]

It looks to me like the one-per-card chips are probably buffer
memories of some sort.

sure, its very simple:

[ATA device IP Core] < BUFFER > [SD Host IP Core]
+ some small management state machine.

You assume that the operation of the buffers is trivial. I suspect it
may not be. Even the ATA interface is non-trivial if you want to
support the faster transfer modes. There's probably a reason why it's
an FPGA and not simply a CPLD.

I'm sure someone could make a more cost-optomized design, but at the
extremes of that, performance may suffer. Of course we could also be
looking at a product where someone plunked down the parts they thought
would be required to make a good solution, but shipped it before
getting their HDL code beyond minimal low-rate functionality.

it really is simple as that, but I would not call it "buffer memory of
some sort"

Oh, and absent information as to what type of "buffer memory" it is,
what exactly would you call it?

 

[[email protected]]

On Jun 21, 1:44 pm, Jan Panteltje <[email protected]> wrote:

eh, if you read my replies, then I did not outrule this to be
implementatble in "3 USD FPGA",
there are not so many FPGA with <= 3 USD price tag. And yes fitting
into to cheapest FPGA
would require near-magical engineering, but could be doable.

Antti

Yes, if you have an 8 bit port, and 8 cards, use the cards in SPI mode
(DO,DI,CS,Clk) one card per bit, then if 200kB / sec you get
16 MB/sec...... not even bad.
Optimizing would bring that to (I think I have seen 800kB/s reported
in SPI)
64 MB /sec read....
So that would use _very_simple logic, why keep to any spec... your own
driver.

 

[Antti]

Yes, if you have an 8 bit port, and 8 cards, use the cards in SPI mode
(DO,DI,CS,Clk) one card per bit, then if 200kB / sec you get
16 MB/sec...... not even bad.
Optimizing would bring that to (I think I have seen 800kB/s reported
in SPI)
64 MB /sec read....
So that would use _very_simple logic, why keep to any spec... your own
driver.

the OP was talking about device that

1) is FULLY ATA compliant
2) is FULLY SD Card compliant
3) uses 2 SD cards both in 4 bit mode to maximize speed

this has nothing todo with "own spec" and SPI mode

Antti

 

[Jan Panteltje]

Yes, if you have an 8 bit port, and 8 cards, use the cards in SPI mode
(DO,DI,CS,Clk) one card per bit, then if 200kB / sec you get
16 MB/sec...... not even bad.
Optimizing would bring that to (I think I have seen 800kB/s reported
in SPI)
64 MB /sec read....
So that would use _very_simple logic, why keep to any spec... your own
driver.

Oops, divide by 10 please ...
Still 6.4 MB/sec would be usable...

 

[Jan Panteltje]

the OP was talking about device that

1) is FULLY ATA compliant
2) is FULLY SD Card compliant
3) uses 2 SD cards both in 4 bit mode to maximize speed

this has nothing todo with "own spec" and SPI mode

Antti

I do not care what OP was talking about, I _do_ care how I could do it.
SDcard spec is expensive you know?
WTF do I need it for if it can be done in an other way.
We were looking for _cheap_ solutions right? Else you just buy a flash disk.

 

[Antti]

I do not care what OP was talking about, I _do_ care how I could do it.
SDcard spec is expensive you know?
WTF do I need it for if it can be done in an other way.
We were looking for _cheap_ solutions right? Else you just buy a flash disk.- Hide quoted text -

- Show quoted text -

WTF ?!

_cheap_ things do not have to be shit, or am I mistaken here?

the 8*SPI in parallel is hardly more expensive in hardware terms then
proper design.

besides the SPI parallel trick need read sync as even same card will
not respond with same clock cycle delay to read commands, so the clock
lines need separate steering. It way more reasonable to make device
that runs 2 SD card in parallel (in 4 bit mode)

Antti