BJT biasing

[riccardo manfrin]

With reference to this network (of common emitter amplifier)

http://4.bp.blogspot.com/_Dw6bXh3FG1Q/R61fbJKINdI/AAAAAAAAAOc/Ae6ExBcFSdI/s320/CE.GIF

I'm trying to bias the BJT through the two tunable parameters

- base resistance R_b
- collector resistance R_c

R_c should be chosen
- small enough to admit the amplification of the whole input signal dynamic (without entering saturation nor cutoff), but
- high enough to support a good current (I_c) to voltage (V_ce) gain and
- small enough to avoid a high output impedance.

Once R_c has been defined to match above criteria, R_b is used to move the Q-point in the middle of the amplifier range by imposing the I_b and consequently the voltage drop on R_c, due to the collector current I_c.

Nevertheless, for a real transistor (I'm using a simple BC237B), the value of h_FE has a very high variance (fairchild datasheet reports a min max value of 120 and 800 respectively, without even providing a typical value).

I would like to know what is the correct procedure to follow in order to find appropriate value of R_b so that the at regime quiescent V_ce = V_cc/2 (so that half of the dynamic is dedicated to positive swinging and the over half to negative).

Regards,
RM

 

[George Herold]

With reference to this network (of common emitter amplifier)



http://4.bp.blogspot.com/_Dw6bXh3FG1Q/R61fbJKINdI/AAAAAAAAAOc/Ae6ExBcFSdI/s320/CE.GIF



I'm trying to bias the BJT through the two tunable parameters



- base resistance R_b

- collector resistance R_c



R_c should be chosen

- small enough to admit the amplification of the whole input signal dynamic (without entering saturation nor cutoff), but

- high enough to support a good current (I_c) to voltage (V_ce) gain and

- small enough to avoid a high output impedance.



Once R_c has been defined to match above criteria, R_b is used to move the Q-point in the middle of the amplifier range by imposing the I_b and consequently the voltage drop on R_c, due to the collector current I_c.



Nevertheless, for a real transistor (I'm using a simple BC237B), the value of h_FE has a very high variance (fairchild datasheet reports a min max value of 120 and 800 respectively, without even providing a typical value).



I would like to know what is the correct procedure to follow in order to find appropriate value of R_b so that the at regime quiescent V_ce = V_cc/2 (so that half of the dynamic is dedicated to positive swinging and the over half to negative).



Regards,

RM

Hi Riccardo, First I wonder if this would be better if posted on sci.electronics.basic.
I'm not much of a transistor level design guy, but the common emitter amp is much improved if you add some emitter resistance. This throws away some gain, but then the whole circuit is not so device dependent. Do you have acopy of "Art of Electronics" by Horowitz and Hill? They do a nice job of getting you started with transistors.

George H.

 

[riccardo manfrin]

Hi Riccardo, First I wonder if this would be better if posted on sci.electronics.basic.

I did not know about this group! I'm make sure all my next questions go there as this definitely *is* basic. my mistake.

I'm not much of a transistor level design guy, but the common emitter ampis much improved if you add some emitter resistance. This throws away some gain, but then the whole circuit is not so device dependent.

I'm documenting about that too (I know it mitigates the thermal runaway through negative feedback). Nevertheless I would like to start with the easiest possible configuration. To this purpose I would like to understand given the specs of a real world datasheet for an npn, what the correct biasing procedure is for a very simple configuration as the posted one.

Do you have a copy of "Art of Electronics" by Horowitz and Hill? They doa nice job of getting you started with transistors.

The TOC looks very interesting. Gonna look for online reading or get my copy.
R

 

[riccardo manfrin]

The TOC looks very interesting. Gonna look for online reading or get my copy.

EHehe I especially love Mr. Transistor Man of figure 2.5 (2nd edition)

 

[George Herold]

I did not know about this group! I'm make sure all my next questions go there as this definitely *is* basic. my mistake.








I'm documenting about that too (I know it mitigates the thermal runaway through negative feedback). Nevertheless I would like to start with the easiest possible configuration. To this purpose I would like to understand given the specs of a real world datasheet for an npn, what the correct biasing procedure is for a very simple configuration as the posted one.

Well 'I think' the emitter resister makes the design easier.

But I'll try without one and then everyone else can correct my mistakes.

So let's say you've got a 20V supply (taking the example from Art of Elec.)and you pikc a 10k ohm collector resistor. Then for mid range you want the collector current to be biased to 1 mA. You then use the Ebber's Moll equation to predict what Vbe voltage will give you that current. It's gonna be somewhere around 0.5 volts..(changes with transistors) So bias somewherenear there and then tweak the bias supply until you've got the 1mA of collector current (10V on collector)


Adding an emitter resistor to the above makes the base voltage more dependent on the emitter resistor and less so on the transistor details.

(at least that's my limited understanding.)

George H.

 

[Robert Lacoste]

"riccardo manfrin" wrote in message

I'm trying to bias the BJT through the two tunable parameters (etc)
...
Nevertheless, for a real transistor (I'm using a simple BC237B), the value
of h_FE has a very high variance

Hello Riccardo,
As you found out, a basic transistor biasing provides a voltage gain very
dependant on the transistor's characteristics (and temperature). In order to
stabilize this gain you need to add a couple of extra parts. Two options are
quite common :

- You can add a serial resistor on the emitter (usually in parallel with a
capacitor tank), and a resistor bridge on the base (emitter-stabilized
biasing)
- You can bias the base through a resistor to the collector instead of to
the power supply (collector-stabilized biasing).

You will find plenty of literature on the subject, but if you need just an
overview you can also buy the last issue of Circuit Cellar magazine (
October 2013), as... I've just published a short tutorial article on BJT
biasing this month ;+)

Friendly yours,
Robert Lacoste
www.alciom.com

 

[Robert Baer]

With reference to this network (of common emitter amplifier)

http://4.bp.blogspot.com/_Dw6bXh3FG1Q/R61fbJKINdI/AAAAAAAAAOc/Ae6ExBcFSdI/s320/CE.GIF

I'm trying to bias the BJT through the two tunable parameters

- base resistance R_b
- collector resistance R_c

R_c should be chosen
- small enough to admit the amplification of the whole input signal dynamic (without entering saturation nor cutoff), but
- high enough to support a good current (I_c) to voltage (V_ce) gain and
- small enough to avoid a high output impedance.

Once R_c has been defined to match above criteria, R_b is used to move the Q-point in the middle of the amplifier range by imposing the I_b and consequently the voltage drop on R_c, due to the collector current I_c.

Nevertheless, for a real transistor (I'm using a simple BC237B), the value of h_FE has a very high variance (fairchild datasheet reports a min max value of 120 and 800 respectively, without even providing a typical value).

I would like to know what is the correct procedure to follow in order to find appropriate value of R_b so that the at regime quiescent V_ce = V_cc/2 (so that half of the dynamic is dedicated to positive swinging and the over half to negative).

Regards,
RM

For absolute reliability, assuming a build of thousands or more, use
a beta of 120.

 

[riccardo manfrin]

- You can add a serial resistor on the emitter (usually in parallel with a

capacitor tank), and a resistor bridge on the base (emitter-stabilized

biasing)

- You can bias the base through a resistor to the collector instead of to

the power supply (collector-stabilized biasing).

Thanks to everyone so far for the answers.
More or less all of you are suggesting a negative feedback to reduce the dependency from transistor specs.
I will study more on this (on the cited Arts of Electronics) and see how the gain can be controlled through these feedback loops (emitter resistor or collector-base resistor).

Thanks again!!!
RM

 

[Robert Baer]

Ae6ExBcFSdI/s320/CE.GIF

dynamic (without entering saturation nor cutoff), but

and

move the Q-point in the middle of the amplifier range by imposing the

I_b and consequently the voltage drop on R_c, due to the collector

current I_c.
value of h_FE has a very high variance (fairchild datasheet reports a

min max value of 120 and 800 respectively, without even providing a

typical value).
to find appropriate value of R_b so that the at regime quiescent V_ce =

V_cc/2 (so that half of the dynamic is dedicated to positive swinging

and the over half to negative).

It's just a matter of cranking thru the math, see this message fro
details...

NNTP-Posting-Date: Thu, 26 Sep 2013 11:41:25 -0500
From: Jim Thompson<[email protected]>
Newsgroups: alt.binaries.schematics.electronic
Subject: Biasing Question from S.E.D - BiasQuestionManfrinSED.pdf
Date: Thu, 26 Sep 2013 09:41:24 -0700
Message-ID:<[email protected]>

But this is NOT a good way to bias a transistor, because of the beta
dependence.

Provide more details about end application, frequency range, etc, and
we can provide a better solution.

Or was this just homework ?

...Jim Thompson

Please forgive me, but without going back to earlier posts and
READing them, i had the stupid impression that you wanted to work on the
basis of maximum output swing without clipping on either end, thus
giving cutoff and saturation as the limits.
The JT drawing referred to does not exactly give the best for this.
The first equation ASS-u-MEs that the transistor is in saturation:
Vcb=0; at least that gives the maximum (peak) voltage for Vbb.
What you want is Ib=(0.5Vcc-Vbe)/(2*hfe*Rc), which will give a
standby (no signal) bias exactly in the middle and thus what would seem
to be what you wanted.
Presumably you do know that full input signal drive (Vbb from zero to
what is given from the JT drawing) will give a rather distorted output.
The smaller the input signal (that is added to Vbb), the lower the
distortion.
As a number of other responders mentioned, adding an emitter resistor
will decrease beta dependency, but also reduce distortion (and modify
equations needed).
Beta range: datasheet specs alluded to are quoted all over the map;
this implies wafer standing up during diffusion, which i think was made
obsolete by Fairchild in the '70s.
Is that part type (and maybe datasheet) from or before that era - and
they have been too lazy to update it?
Dig back in past, or see if date on datasheet is of that era.
Methinks the beta range is more narrow and rather high (100s and up).
Buy a few now and then to get different date lots, and test them.

 

[Spehro Pefhany]

With reference to this network (of common emitter amplifier)

http://4.bp.blogspot.com/_Dw6bXh3FG1Q/R61fbJKINdI/AAAAAAAAAOc/Ae6ExBcFSdI/s320/CE.GIF

I'm trying to bias the BJT through the two tunable parameters

- base resistance R_b
- collector resistance R_c

R_c should be chosen
- small enough to admit the amplification of the whole input signal dynamic (without entering saturation nor cutoff), but
- high enough to support a good current (I_c) to voltage (V_ce) gain and
- small enough to avoid a high output impedance.

Once R_c has been defined to match above criteria, R_b is used to move the Q-point in the middle of the amplifier range by imposing the I_b and consequently the voltage drop on R_c, due to the collector current I_c.

Nevertheless, for a real transistor (I'm using a simple BC237B), the value of h_FE has a very high variance (fairchild datasheet reports a min max value of 120 and 800 respectively, without even providing a typical value).

I would like to know what is the correct procedure to follow in order to find appropriate value of R_b so that the at regime quiescent V_ce = V_cc/2 (so that half of the dynamic is dedicated to positive swinging and the over half to negative).

Regards,
RM

This is not the ideal way to bias a transistor, but it's perfectly
do-able.

The particular part you mention is binned into three categories-
A, B, C. Say you buy the B version, hFE is guaranteed to be between
180 ~ 460 at 2mA Ic & 25°C Tj (it doesn't change much with collector
current from 1mA up to 10's of mA). It can change significantly with
junction temperature (including self-heating).

Say you use a relatively high Vcc and Vbb, 12V, say. The approximation
Vbe = 0.6V for the transistor active then is pretty good, and we can
say that Ib ~= (Vcc - 0.6V)/Rb

If you want an ouptut impedance of a few K, you can choose nominal Ic
to be 2mA, so with the output voltage centered, a 3K resistor is
called for.

The only thing left is to pick a Rb st the extremes of beta give a Vc
equally far from either rail. Say we allow 20% for temperature effects
(modest temperature variations), so hFE will be between 144 and 552.

That results in an Rb of 1.983M ohms, and Vc will be between ~2.48V.
and ~9.51V, so an output voltage of about 5V p-p would just be
clipping, worst-case. If you only needed a volt or two p-p output,
this could be acceptable (over a narrow temperature range, limited to
this particular transistor type including bin code).