Sure,
From reading the ECP.pdf document,the data lines is shared for both
data and command (referred as data cycle or command cycle). Line
HostAck is used to determine the cycle.
On the command cycle, 2 format is possible. One format is RLE and the
other is address. Bit 7 is used to determined which format is
selected. RLE will not be used in this application. Only the Address
part is used. With 7 bits, I can used up to 128 address to select
different function internal to the Altera FPGA. Also, in the command
cycle, the data line will flow only in one direction(PC to my
peripheral device).
Good so far. Note that I've never used an Altera FPGA, so there
may be differences in the implementations.
On the Data cycle, both direction on the data line will be used.
Ok, I suspected that. ;-)
There are 3 different function the FPGA will perform. Let call these
function A, B, C and D.
Function A (Write Only, PC to Device)
First, the PC Parallel Port will address the FPGA for function A. Then
loads via Data cycle, 2 bytes in the FPGA. The two bytes will appear
on 16 pins of the FPGA. The a CS strobe is pulsed on a separate pin
of the FPGA.
Questions:
The 'CS' is strobed after the second byte appears?
How long is CS?
Is handshaking on CS required?
Do the two bytes have to appear at the output at the same time or
can they appear at any time before CS?
Function B (Write Only, PC to Device)
The PC Parallel Port will address the FPGA for function B. Then loads
via Data cycle, 1 bytes into the FPGA. The 1 byte is then clocked out
of the FPGA serially at 2 MHz as a SPI interface.
Separate output from Function A?
Addresses?
How do I know the difference between Function A and Function B?
2MHz, where? Do you have an oscillator? What frequency?
What about overruns/underruns? Frameing?
Function C (Write Only, PC to Device)
The PC Parallel Port will address the FPGA for function C. Then loads
via Data cycle, 1 bytes into the FPGA. Each bits of this byte will
control the direction of the pins of funtion D.
Simple enough.
Function D (Write and Read, PC to Device or Device to PC)
WRITE OPERATION:
The PC Parallel Port will address the FPGA for function D, Write
operation. Then loads via Data cycle, 1 bytes into the FPGA.
Depending on the control bits of function C, some or all of the bit of
the loaded bytes will appear on up to 8 output pins of the FPGA.
Looks simple.
READ OPERATION:
The PC Parallel Port will address the FPGA for function D, READ
operation. The FPGA will read the same 8 pin described above for the
WRITE operation and is then transferred to the data lines of the PC
Parallel Port . The PC then reads the 8 bit data.
Direction bits? Does this read read back the bits written (and set
to output) in D-Write above?
As I see it, I will be OK with the Function part of the FPGA. But,
however simple the Parallel Port is in this application, I need help
on the Parallel communication protocol part. That is, how to make
the data available to and from the FPGA functional part.
That's pretty easy. When the port is writing to the FPGA you set
the FPGA drivers to 'Z'. When reading the FPGA they're driven by
the input pins on your Function D-Read port. Something like:
ParallelPort <= PortD
WHEN FunctionD_Read = '1'
ELSE (others=>'Z');
This may have timing problems so depending on Altera's I/O you
should incorporate a flipflop into the I/O cell (at least with
Xilinx this works better):
PPort: PROCESS (Clock, Reset)
BEGIN
IF Reset = '1'
THEN
ParallelPort <= (others=>'Z');
ELSIF Rising_edge(Clock)
THEN
IF FunctionD_Read = '1'
THEN
ParallelPort <= PortD;
ELSE
ParallelPort <= (others=>'Z');
END IF;
END IF;
END PROCESS;
