Answers to old-fart electronics quiz

[Jan Panteltje]

I read in sci.electronics.design that Jan Panteltje
01.evisp.enertel.nl>) about 'Answers to old-fart electronics quiz', on
Mon, 26 Jan 2004:

My 50 W PA amplifiers with KT88s suffered real thermal runaway on a hot
day until I improved the ventilation. Real thermal runaway is when the
control grid gets hot enough to start emitting electrons - it doesn't
need many to cause the cathode current to skyrocket. Result - burned out
cathode resistors.

Yep, and I was thinking:
take that rectifier tube, once the anode gets hot enough, it will emit too, so basically
the diode becomes conducting both ways (with interesting effects).
But I have not tried that.
In the old Ampex vr1000 (or1500 dont remember) studio quadruplex video recorders
(1968 or so) the power tubes for the head drive were upside down
cooled with a fan, if the fan failed the tubes unsoldered themselves from the sockets and
dropped to the bottom, breaking the circuit.
Was a frequent error
Jan

 

[John Woodgate]

I read in sci.electronics.design that Spehro Pefhany <Spehro@Pefhany.?>

Is there any technical reason they can't be put internally, if chip
designers could just get over their bias against (external, in this
case) inductors? AFAIK, internal regulators are mostly charge pumps or
linear.


Gordon, Michael or Benjamin?

Or even 'Old'?

 

[John Woodgate]

I read in sci.electronics.design that Jan Panteltje
01.evisp.enertel.nl>) about 'Answers to old-fart electronics quiz', on
Tue, 27 Jan 2004:

Yep, and I was thinking:
take that rectifier tube, once the anode gets hot enough, it will emit
too, so basically the diode becomes conducting both ways (with
interesting effects). But I have not tried that.

Anodes are often coated with carbon to minimise secondary emission, so
primary emission would also be very low.

 

[Allan Herriman]

My current design has the following rails:

+12V (fans)
+5V (optics)
+3.3V (some logic, uP, optics, ASIC I/O)
+2.5V (FPGA I/O)
+2.5V (FPGA "aux")
+2.0V (ASIC core)
+1.8V (optics)
+1.5V (FPGA core)

I used 74ALVC164245s to pass signals between the 3.3V uP I/O and the
2.5V FPGA I/O.

Regards,
Allan.

 

[John Larkin]

On Tue, 27 Jan 2004 10:37:56 -0700, the renowned Jim Thompson
^^^^^^^^^^^
Gretzky?


Then a current-mode buck switching regulator with external inductor
should be possible, right? Or is there a problem getting enough gate
drive on the "pass" transistor? The diode to ground could be an
internal MOSFET or could be an external Schottky. Or is all this a
stupid suggestion because MOSFET acreage costs much less than VLSI
acreage? Or for some other reason?

Best regards,
Spehro Pefhany

Google "point of load alliance"

Sounds like people are working on this problem.

John

 

[John Larkin]

My current design has the following rails:

+12V (fans)
+5V (optics)
+3.3V (some logic, uP, optics, ASIC I/O)
+2.5V (FPGA I/O)
+2.5V (FPGA "aux")
+2.0V (ASIC core)
+1.8V (optics)
+1.5V (FPGA core)

I used 74ALVC164245s to pass signals between the 3.3V uP I/O and the
2.5V FPGA I/O.

Regards,
Allan.

Yecch. Looks like the return of glue logic. All you need now is some
ECL and three or four analog rails.

I have a 68332 uP running at +5 and a big bga Xilinx that uses 3.3 for
the I/O cells. We connected them through 200 ohm resistors, which
seems to work. If the FPGA were 2.5 I/O, we'd have to do something
else.

This is getting crazy.

John

 

[Ian Buckner]

message >

Yecch. Looks like the return of glue logic. All you need now is some
ECL and three or four analog rails.

I have a 68332 uP running at +5 and a big bga Xilinx that uses 3.3 for
the I/O cells. We connected them through 200 ohm resistors, which
seems to work. If the FPGA were 2.5 I/O, we'd have to do something
else.

This is getting crazy.

John

Yep, got the analog rails and ECL as well. Add a 1V rail for LVDS
bias....

I do like the term "big bga" ;-)

Regards
Ian

 

[Allan Herriman]

Yecch. Looks like the return of glue logic. All you need now is some
ECL and three or four analog rails.

I actually do have some ECL parts, but I'm running them from the +3.3V
supply. There are also two 3.3V analog rails (that I didn't mention)
supplied by independent linear regulators.

There's also a +1.25V reference for some SSTL rams.

This is getting crazy.

Crazy or not, this is what was needed for the design. The power
supplies are not a major part of the cost for this particular design.
(This is not a consumer product.)

For me, the worst bit is running out of planes within the PCB. We
already have 14 layers, and it we add any more it wouldn't fit into an
edge connector. Either that, or the layers would be so thin that
traces of a useful impedance would be unreasonably narrow.

Regards,
Allan.

 

[Allan Herriman]

I actually do have some ECL parts, but I'm running them from the +3.3V
supply. There are also two 3.3V analog rails (that I didn't mention)
supplied by independent linear regulators.

There's also a +1.25V reference for some SSTL rams.


Crazy or not, this is what was needed for the design. The power
supplies are not a major part of the cost for this particular design.
(This is not a consumer product.)

For me, the worst bit is running out of planes within the PCB. We
already have 14 layers, and it we add any more it wouldn't fit into an
edge connector. Either that, or the layers would be so thin that
traces of a useful impedance would be unreasonably narrow.

Another problem with having so many rails is testing and monitoring.
I added an LM87 (an SMBus voltage and temperature monitor chip) to
measure the voltages on some of the rails:

cat /proc/lm87

+2V0 = [9c] 2.031 V
+2V5 = [b1] 2.489 V
+3V3 = [bd] 3.248 V
+5V0 = [cb] 5.286 V
+12V0 = [00] 0.000 V
VCCAUX = [b1] 2.489 V
VCCINT = [9a] 1.504 V
+1V8 = [b7] 1.787 V
FPGA = [22] 34 C
LM87 = [1d] 29 C

Regards,
Allan.