Another discrepancy (LTspice/switchcad3)

[Robert Baer]

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:

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TEXT 448 408 Left 0 ;N006
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[Mike Engelhardt]

Robert,

The results are way off.

The simulation is probably right around correct. That
FET and diode have capacitance. Below is a working 1619
circuit you might use as stating point.

--Mike

--- 1619.asc ---


Version 4
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TEXT 1840 1024 Left 0 !.tran 4m startup

 

[Helmut Sennewald]

----- Original Message -----
From: "Robert Baer" <[email protected]>
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values are
from a real circuit, and seem to be reasonably close to calculated values
using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:

Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut

 

[Robert Baer]

Robert,




The simulation is probably right around correct. That
FET and diode have capacitance. Below is a working 1619
circuit you might use as stating point.

--Mike

------------ SNIPped for brevity ---------
Adding a small capacitance has no effect.
Even altering the ideal inductor to a resistive inductor with
parallel capacitance has no effect.
I will try your 1619 circuit later; i use a different OS for mail/NGs
than for "fancy" work (different drives also).

 

[Robert Baer]

----- Original Message -----
From: "Robert Baer" <[email protected]>
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)





Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut

**1. The resistive divider is purposeley set for a larger than possible
voltage; to see what SPICE would do.

**2. The real circuit will output about 1000V with a 4V inductor supply;
i do not think this is relevant.

**3. For real parts, that is part of what happens. I tried making the
inductor more complex by adding a small series resistor and then
paralling that combo with a small capacitor. That modification made
absolutely zero difference.

**"4". If i take my P17/8-3C18 core and wind a "primary" of 56 turns and
then continue winding for another 73 turns (autoformer "secondary" of
129 turns), i get about 1800VDC with a doubler (very close to the
peak-to-peak voltage at xfmr output), with a 58Meg load (worst case PMT
divider); voltage at inductor "top" at 30V but can range from about 5V
to 200V (actually more than 200V but my bypass cap is rated at 200V).

** However, nothing you have mentioned addresses any of the major
discrepancies seen.

 

[Mike Engelhardt]

Robert,

Adding a small capacitance has no effect.

But that doesn't remove the capacitance that's already
swamping the circuit. The problem is the circuit design,
not the models.

I will try your 1619 circuit later

That one works. Notice that that SMPS topology is
a boost. To get higher output voltage, you might try
a tapped-inductor boost. That will reduce the voltage
rating required of the MOSFET and make the circuit
less sensitive to its capacitance. If you're not really
after a SMPS, but some high impedance high voltage,
you can probably get a chopped square wave working
into a diode voltage multiplier to work. That gets rid
of the problem of getting high impedance energy
storage inductors with little stray capacitance.

-Mike

 

[Robert Baer]

Robert,




But that doesn't remove the capacitance that's already
swamping the circuit. The problem is the circuit design,
not the models.

There is no problem with the design.
Both theory and practice show that when a voltage is presented across
an inductor, that the current starts at zero and increases in the
standard L/R exponential "decay" to maximum, the assumption is a linear
inductor. Classical definition of an inductor!
The problem, is that the model does *not* show that.
And a pF or two cannot "swamp" anything here.

That one works. Notice that that SMPS topology is
a boost. To get higher output voltage, you might try
a tapped-inductor boost. That will reduce the voltage
rating required of the MOSFET and make the circuit
less sensitive to its capacitance. If you're not really
after a SMPS, but some high impedance high voltage,
you can probably get a chopped square wave working
into a diode voltage multiplier to work. That gets rid
of the problem of getting high impedance energy
storage inductors with little stray capacitance.

-Mike

I think i mentioned the word "autoformer" somewhere; have a
Ferroxcube 14/8-3C81 core with 56 turns pri and 129 total (secondary),
and get about 1800V DC with about 58Meg load.
Inductor supply can run from about 5V to 200V (bypass cap rating);
looks like i could get up to a 400V input.

I tried the square wave idea (variable amplitude, variable frequency)
idea with a CFL transformer.
Worked fine, efficency improved as i drove it from 1/7, to 1/5, to
1/3 and at "resonance".
Those transformers are very lossy at "high" frequencies; resonance
near 300KHz for the Cooper CTX210407 and two other randomly chosen CFL
xfmrs.
Input square wave, output slightly clipped sinewave; re-winding the
primary drive made no major difference, except with fine wire and many
turns, i saw I*I*R losses (efficency went from 30 percent area to 16
percent).

BUT. Again, there was *no* instant current spike in the amps; there
is clearly an error in the modeling, and i do not see it.

 

[Mike Engelhardt]

Robert,

There is no problem with the design. Both theory and
practice show that when a voltage is presented across
an inductor, that the current starts at zero and increases in the
standard L/R exponential "decay" to maximum, the
assumption is a linear inductor. Classical definition of
an inductor! The problem, is that the model does *not*
show that.

The current does ramp in the inductor when there's voltage
across it in the simulation. But the capacitance(and other
problems) prevents your circuit "design" from working.

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged. MOSFET catastrophic failure is not modeled
in LTspice in hope that this allows you to separately debug
the design and then find parts that don't die in the
circuit's operation.

And a pF or two cannot "swamp" anything here.

Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

Regards,

--Mike

 

[Jim Thompson]

Robert,
[snip]

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged. [snip]

Regards,

--Mike

"Designers" are what keep me in the "chips" ;-)

...Jim Thompson

 

[Mike Engelhardt]

Robert,

Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

It might be illustrative to see your circuit operate
without the capacitance so severely swamping the
circuit. Below is your circuit except ideal switches
are used and the SMPS topology is corrected to a
true boost. This is not a practical circuit design,
because you can't buy the parts to make it go, but
a tapped boost topology would remove the problem
of the MOSFET capacitance.

Regards,

--Mike

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[Robert Baer]

Robert,




The current does ramp in the inductor when there's voltage
across it in the simulation. But the capacitance(and other
problems) prevents your circuit "design" from working.

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged. MOSFET catastrophic failure is not modeled
in LTspice in hope that this allows you to separately debug
the design and then find parts that don't die in the
circuit's operation.




Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

Regards,

--Mike

I had thought that i made it clear that i have a *working* circuit.

Neither my model nor the "1619" model show a current ramp, period.
I took a simple test fixture that uses a FET with the drain to a fat
wire just long enough for a Tek current probe, then to the test
inductor, then to bypassing, where the inductor supply voltage is applied.
The gate is driven by an HP3312A waveform generator; adjustable rep
rate and pulse width.
Using a 10uH inductor (closest i had to the 12uH in the "1619"
model), and a 3.30V supply, i saw the following:
1) IRFBG20, 1000V rating, "miller" 22nCoul: linear current *ramp* to
600nSec, 60ma at 300nSec. Gate off at 500nSec was "slow" with a sloppy
flyback 20V rounded pulse.
2) IRLZ24N, 55V rating, "miller" 8.5nCoul: linear current *ramp* to
600nSec, 70ma at 300nSec. Gate off at 500nSec was fairly snappy with a
classic flyback 34V flattish pulse.
Case #2 works closer to theory for two reasons: a) the FET is turned
on harder with a 10V gate drive because it is a logic FET, and b) lower
miller capacitance makes for faster turnoff.

The models show *square waves* !!
The models show *AMPS* of current !!
The model does not show anything near reality!
The classic definition of an inductor is a (linear) component that
opposes a change of current.

 

[Robert Baer]

Robert,

[snip]

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged.
[snip]

Regards,

--Mike

"Designers" are what keep me in the "chips" ;-)

...Jim Thompson

Please be kind to read my response to Mike ("above").
If you can tell me what i did wrong in the model, please let me know.
Once the model shows real current ramping in an inductor, then i
think that the rest will be OK.

 

[Jim Thompson]

Robert,

[snip]

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged.
[snip]

Regards,

--Mike

"Designers" are what keep me in the "chips" ;-)

...Jim Thompson

Please be kind to read my response to Mike ("above").
If you can tell me what i did wrong in the model, please let me know.
Once the model shows real current ramping in an inductor, then i
think that the rest will be OK.

Have you checked your _simulated_ schematic against the hardware?

...Jim Thompson

 

[Helmut Sennewald]

**1. The resistive divider is purposeley set for a larger than possible
voltage; to see what SPICE would do.

**2. The real circuit will output about 1000V with a 4V inductor supply; i
do not think this is relevant.

**3. For real parts, that is part of what happens. I tried making the
inductor more complex by adding a small series resistor and then paralling
that combo with a small capacitor. That modification made absolutely zero
difference.

**"4". If i take my P17/8-3C18 core and wind a "primary" of 56 turns and
then continue winding for another 73 turns (autoformer "secondary" of 129
turns), i get about 1800VDC with a doubler (very close to the
peak-to-peak voltage at xfmr output), with a 58Meg load (worst case PMT
divider); voltage at inductor "top" at 30V but can range from about 5V to
200V (actually more than 200V but my bypass cap is rated at 200V).

** However, nothing you have mentioned addresses any of the major
discrepancies seen.

Hello Robert,
I did some more simulations with some components changed to get
more reliable results.
Maybe I see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate output of
the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

Best regards,
Helmut

 

[Helmut Sennewald]

Hello Robert,
I did some more simulations with some components changed to get
more reliable results.
Maybe I see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate output of
the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

Best regards,
Helmut

Hello Robert,

I already have got an answer from Mike. He told me
that these complex output pulses may be caused by different
reasons.

Best regards,
Helmut

------- Begin answer from Mike --------

That happens in really bad SMPS designs.
There's lots of ways you can get double/triple
pulses that are due to design flaw(s).
You have to deal with minimum on time,
maximum off time, slope compensation,
capacitive current spikes, blanking times,
and loop instabilities. SMPS have all sorts
of non-linear oscillation modes.

-------- End answer from mike -------------

 

[Mike Engelhardt]

Robert,

I had thought that i made it clear that i have

That wasn't clear to me because the circuit you
posted clearly does not work.

The models show *square waves* !!
The models show *AMPS* of current !!
The model does not show anything near reality!

The difference is that you are using a different
MOSFET in simulation then the bench. The simulation
results would agree with using a the MOSFET you have
on that schematic you posted. Now you're here talking
about different MOSFETs.

LTspice is showing what reality would look like for the
parts you have in the schematic. Your bench circuit is
entirely different. The schematic is totally shorted
out with capacitance, your bench circuit apparently
not. See the corrected schematic I posted with
capacitance-free switches.

The classic definition of an inductor is a (linear)
component that opposes a change of current.

And the simulation you posted does show that. But you
have to look at the current in the inductor and
the voltage across it. Neither the sense resistor
nor the switch current will follow that ramp, because
capacitive displacement currents swamp the inductor
current ramp.

--Mike

 

[Mike Engelhardt]

Helmut,

I did some more simulations with some components
changed to get more reliable results. Maybe I
see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate
output of the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

That's what happens with really poorly designed
SMPS's. There's lots of ways you can get
double/triple pulses that are due to design
flaws(s). You have to deal with min and max
on/off times, slope compensation(which nearly
swaps Robert's current slope with the 1mH
inductor moving the low frequency compensation
pretty close to voltage mode), and loop
instablies near the switching frequency. SMPS
have all sorts of non-linear oscillation modes.

But now it looks like the problem is that Robert
is using a different MOSFET on the bench than
in the schematic.

--Mike

 

[Robert Baer]

Jim Thompson wrote:

Robert,


[snip]


Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged.

[snip]


Regards,

--Mike



"Designers" are what keep me in the "chips" ;-)

...Jim Thompson

Please be kind to read my response to Mike ("above").
If you can tell me what i did wrong in the model, please let me know.
Once the model shows real current ramping in an inductor, then i
think that the rest will be OK.

Have you checked your _simulated_ schematic against the hardware?

...Jim Thompson

Absolutely.
I went further; i made a simple model for TopSpice and it works; the
same model for LTspice/Switchcad3 does not.
Now one may bitch that the FET used in the LTspice case is not the
same, but that is not a relevant arguement.
I "proved" that by my test fixture using first a 1000V FET (IRFBG20)
and then a logic FET (IRLZ24N).
Practice meets theory; a *ramp* of current when the gate is driven,
and a *pulse* of voltage right after the FET turns off.
No junk square waves, no tens of amps in the drain.

*** TopSpice ***
SWMODE MOSFET TopSpice 1993 rev 2.6 (for DOS)
..OPTIONS ACCT LIST NODE OPTS LIMPTS=2000000
..TEMP 27
* ini amp Td Tr Tf PW Per
VG 1 0 PULSE( 0 10 0us 0.01us 0.01us 19.98us 100us)
VL 0 5 -10V
LL 5 4 1000UH
* D G S
X1 4 1 0 IRFBG20
..TRAN 0.1US 25US
..PRINT TRAN/ALL V(4) I(VL)
..SUBCKT IRFBG20 1 2 3
**************************************
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
**************************************
* Model generated on Mar 14, 97
* MODEL FORMAT: SPICE3
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
..MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=4.19558 LAMBDA=0.00317546 KP=1.10594
+CGSO=4.97244e-06 CGDO=1e-11
RS 8 3 0.226968
D1 3 1 MD
..MODEL MD D IS=2.60701e-11 RS=0.0402674 N=1.17581 BV=1000
+IBV=0.00025 EG=1 XTI=1 TT=0
+CJO=4.31956e-10 VJ=2.22169 M=0.9 FC=0.5
***RDS 3 1 1e+07
RD 9 1 6.20884
RG 2 7 4.12
D2 4 5 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
..MODEL MD1 D IS=1e-32 N=50
+CJO=1.29076e-09 VJ=0.888177 M=0.9 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
..MODEL MD2 D IS=1e-10 N=0.456748 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 1.29076e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
..MODEL MD3 D IS=1e-10 N=0.456748
..ENDS IRFBG20
..SAVE
..END
**************

*** for LTspice/Switchcad3 ***
Version 4
SHEET 1 880 680
WIRE -176 208 -176 112
WIRE -48 352 -48 320
WIRE 80 320 -48 320
WIRE 128 112 -176 112
WIRE 128 240 128 192
FLAG -176 288 0
FLAG 128 336 0
FLAG -48 432 0
SYMBOL voltage -176 304 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value -10V
SYMBOL ind 112 96 R0
SYMATTR InstName L1
SYMATTR Value 1000µH
SYMBOL nmos 80 240 R0
SYMATTR InstName M1
SYMBOL voltage -48 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 0 0.01U 0.01U 19.98U 100U)
TEXT 144 224 Left 0 ;N003
TEXT -258 506 Left 0 !.tran 0 25US 0 .1U
TEXT -176 72 Left 0 ;** PRINT TRAN/ALL V(N003) I(V1)
***************

 

[Jim Thompson]

I'm busy, so it may take a few days, but I'll give it a try in PSpice.

...Jim Thompson

 

[Robert Baer]

Hello Robert,

I already have got an answer from Mike. He told me
that these complex output pulses may be caused by different
reasons.

Best regards,
Helmut

------- Begin answer from Mike --------

That happens in really bad SMPS designs.
There's lots of ways you can get double/triple
pulses that are due to design flaw(s).
You have to deal with minimum on time,
maximum off time, slope compensation,
capacitive current spikes, blanking times,
and loop instabilities. SMPS have all sorts
of non-linear oscillation modes.

-------- End answer from mike -------------

Errr...I have reduced the problem to the most simple possible; a FET
driving an inductor. *No* SMPS, just a basic circuit.
*Same* problem.
See an earlier response with that simple circuit *working* in
TopSpice (1mH, 20uSec, 10V), virtually identical to practice, but
garbage square waves in LTspice/switchcad3.
As i mentioned earlier, i used my simple test fixture (to emulate the
"1619" example) using a 10uH inductor and 3.3V supply and got a *ramp*
of current to a few hundred mA - just like theory (and the *definition*
of an inductor). But LTspice/switchcad3 gives square waves.
Different inductance and time scales, but the same result for practice.
Modelling with a given SPICE program is consistent for that program,
but TopSpice echos practice and the other does not.
I guess for this, i will have to scrap LTspice/switchcad3.