D
Didi
But the PCI bus doesn't run at GHz and has lots of overhead for a single
Sounds like the delay has been down to bridging to/from
the PCI bus, PCI is much faster than that. Maximum latencies
can get large because of bus (req/grant etc.) delay, but
minimum (when the bus is free or owned) are much below
1uS.
However, for a monstrous mess like the x86 your figures
are about the best one could expect, sound quite reasonable.
Dimiter
cycle I/O access. On the same system the minimum width of a software
generated pulse on an I/O line was about 4us.
Sounds like the delay has been down to bridging to/from
the PCI bus, PCI is much faster than that. Maximum latencies
can get large because of bus (req/grant etc.) delay, but
minimum (when the bus is free or owned) are much below
1uS.
However, for a monstrous mess like the x86 your figures
are about the best one could expect, sound quite reasonable.
Dimiter