The pinout is given as D G S when viewed from the front.
Depends on what you decide is the front. For me the front would be the flat side with the labeling on it. With the pins facing down (so you can read the print), the correct sequence is S G D (as per datasheet):

But reversing D and S would not destroy the opamp.
I imagine there needs to be resistors added
I wouldn't know where and why. You can short the opamp's input pin to gnd and this should not destroy the opamp. I guess something else happened.
The real issue is that you selected an unsuitable FET. Your choice is a depletion JFET, not a MOSFET. A JFET (Junction FET) has no isolating oxide layer between gate and channel. Isolation is provided by a pc-junction which has to be reverse biased (negative V
GS). When you applied a positive gate voltage, the pn-junction was forward biased and the modulating signal (f
carrier in post #3) was directly connected to the input of the opamp via the gate-drain diode of the JFET. This may have caused the defect in the opamp if the input voltage from the carrier signal was too high.
Apart from that the 2N3819 is designe fore VHF/UHF applications and not well suited for use with comparatively low frequency signals.
Your image in post #3 shows an enhancement MOSFET (2n7002) which has an isolated gate and requires a positive V
GS to be turned on. It is designed for switching applications. Controlling it with a sine on the gate will not produce the expected result: the threshold voltage is somewhere between + 1 V and + 2.5 V (note the wide range). Simply stated: below that the transistor is off, above that the transistor is on. This is why the image in post #3 shows a square wave as the carrier signal.
You can use the 2N3819 as a voltage controlled resistor with a sinusoidal input, see e.g.
this app note.
Or, if you can accept a square wave carrier, use the 2N7002 as per the original schematic.