4017 with clock input but without power supply

[osterchrisi]

Hey!

I want to shut the output of a 4017 completely off but I can't think of any other means that simply cutting the power supply off the chip to stop it. Because even if you cut away the clock signal or reset the chip all the time it still is HIGH on the last step or the first step.

Do you think this will damage the chip over a long time? The clock signal is then still present at the input. It worked in a few tests now but I'm wondering about long-term symptoms.

 

[(*steve*)]

if you remove power to the chip, you may find that it actually stays powered if there are any inputs at a logic HIGH state. The input protection diodes will shunt power from there to the rest of the chip.

If your input can't draw sufficient current from the logic signal, then it may appear to be turned off.

It's probably not a great method, although I have seen it done. You need to beware of latchup and prevent it happening.

 

[JimW]

You need to define what you mean by "off".

Digital low on all the outputs?
High impeadance to ground and VCC?
High impeadance to all other outputs?

This may affect what the correct solution is. Buffering all of the outputs you are interested in with an analog switch is a good start, but may be overkill for what you really want.

But I have done the supply switching trick. Although it was a one out project with no volume production. So I can't gauarantee anything over a large number of chips or multiple vendors of the 4017 parts.

As Steve said, I would be concerned about the edge cases of a input switching while the chip power was coming on. I could see a variety of odd output conditions occuring. But I doubt they would be fatal or anything more than transient. So if you were willing to issue a reset after power has settled, and then wait for some (unknown) period of time for the outputs to settle, then I would think you would be OK.

JimW

 

[(*steve*)]

One edge case is latchup, and that can be fatal as it essentially gives you a short across the power supply pins. If you want to hear an Indian lecture from the 90's on the topic, you will find it here.

There are various techniques which can minimise the effect, but do you know that your devices have this?

 

[osterchrisi]

Thanks for your input guys. With 'off' I meant LOW on all outputs in fact. Although I figured out now anyway that I will have to switch off both the clock signal and the power supply with a switching chip because I have a feedthrough from the clock.

I'm using this device for musical purposes as a step sequencer by the way. So if I want it off I simply mean that it should not send any signal to my CV mixer...

 

[JimW]

As far as latch up goes, I can always go back and review some of my notes on it, but I seem to remember that it can only occur (or most likely to occur) if the CMOS chip has both Q and Q# outputs, and then you need supply transients or improper set up and hold times to the clock. The 4017 doesn't have both inverting and non-inverting outputs.

If you just want to have all the outputs low, then use a combination of the 4017 RESET line and some combinatorial logic to the Q0 output. NEWQ0 = (Q0 * RESET# ) This has some minor propogation delay issues but if youa re dealing in audio then it shouldn't be an issue.

 

[osterchrisi]

Ok, I solved the problem now and thought you might be interested: By connecting the RESET pin of the 555 driving the 4017 to ground and at the same time cutting the power supply for the 4017 you can make all the outputs go LOW.
I did that with a spare analog switch on a 4016 and a transistor as a NOT gate. Thanks for your input once again.

 

[(*steve*)]

As far as latch up goes, I can always go back and review some of my notes on it, but I seem to remember that it can only occur (or most likely to occur) if the CMOS chip has both Q and Q# outputs, and then you need supply transients or improper set up and hold times to the clock. The 4017 doesn't have both inverting and non-inverting outputs.

We're straying from the original point, but I think you may be thinking about metastable states.

Latchup can occur when the input or output of an inverter is pulled higher or lower than the supply rails.

It triggers a parasitic SCR formed by the pair of mosfets. If this gets triggered, you have a low impedance path from supply rail to supply rail. Typically it requires a power cycle to reset.

There are various methods of making CMOS more resistant to latchup, but you have to dive deeply into the specs to find out if it applies to your choice of device.

 

[duke37]

Somewhat off topic. I have a 4017 which I want to use to make a traffic light sequencer.
Is it necessary to reset it at on power up or will it sort itself out if it starts in a strange mode?

 

[(*steve*)]

It's always best to ensure that logic gets a definite reset on power on.

It's also wise to ensure that any logic state (even ones you can't get to normally) will eventually transition to a normal state.

The answer to both of your questions is yes.