S
siva
Hi,
to convert the 1 mhz input to 1 hz output, how many no. of D-flip flop
should i use?
Thanks
regards
siva
to convert the 1 mhz input to 1 hz output, how many no. of D-flip flop
should i use?
Thanks
regards
siva
siva said:Hi,
to convert the 1 mhz input to 1 hz output, how many no. of D-flip flops
should i use?
Thanks
regards
siva
Fred said:Approximatly 19,931568569324174087221916576936
None. Use 6 divide by 10 counters.siva said:Hi,
to convert the 1 mhz input to 1 hz output, how many no. of D-flip flops
should i use?
Thanks
regards
siva
Tam/WB2TT said:None. Use 6 divide by 10 counters.
Tam
siva said:Hi,
to convert the 1 MHz input to 1 Hz output, how many no. of D-flip flops
should I use?
If you have to ask the question, the honest answer is none - you are
highly unlikely to get it to work.
If you learnt quite a lot, you could probably do it with 21 - using 20
to make a 20-bit counter, which can count up to 1048576, and the last
one to hold the reset pulse for one period of the 1MHz clock. You'd
need quite a bit of combinational logic to persuade the D-types to act
as counters, and some more to initiate the reset pulse at a count of
999,999.
Fairly trivial if you buy your D-type bistables in a programmable logic
chip, otherwise an absolute nightmare to wire up.
If you have to ask the question, the honest answer is none - you are
highly unlikely to get it to work.
If you learnt quite a lot, you could probably do it with 21 - using 20
to make a 20-bit counter, which can count up to 1048576, and the last
one to hold the reset pulse for one period of the 1MHz clock. You'd
need quite a bit of combinational logic to persuade the D-types to act
as counters,
and some more to initiate the reset pulse at a count of
999,999.
Fairly trivial if you buy your D-type bistables in a programmable logic
chip, otherwise an absolute nightmare to wire up.
Keith said:D <= Q-bar isn't a lot of combinatorial logic. Just do a ripple
counter, with Ck(n)<= Q(n-1) and D(n)<=Q(n).
True, if exactly divide by 1E6 is needed (5% error isn't
tollerated).
Programmable logic is the easiest way, but 8-bit counters with
parallel load and terminal-count can be had (e.g. 74*579). Wire
the desired count to the inputs and do an and use TC to load the
count. Details left to the OP.
Hi,
to convert the 1 mhz input to 1 hz output, how many no. of D-flip flops
should i use?
Thanks
regards
siva
Somebody said 20,21 flipflops .. naw you can use much less . A
typical divide by 10 counter has 4flipflops and so If you don't feel
like cracking your brains get 3 divide by 10 counters , cascade them
and you got your 1pulse/sec signal.
If you want to design the thing let me know
Ulp!
"Go easy on the whisky "
theJackal said:Somebody said 20,21 flipflops .. naw you can use much less . A
typical divide by 10 counter has 4flipflops and so If you don't feel
like cracking your brains get 3 divide by 10 counters , cascade them
and you got your 1pulse/sec signal.
If you want to design the thing let me know
Six decades oh yeah ... I'd hope to live over that age though.You're only halfway there. Hints: 3*4=12, 12<20, and 1MHz -> 1Hz
is *six* decades.
its never too late over here .Indeed, it's a little early for such.
3 divide by 10 counters gets 1 MHz down to 1kHz.
6 divide by 10 counters gets you to 1 Hz, with 24 flip flops.
If you have to ask the question, the honest answer is none - you are
highly unlikely to get it to work.
If you learnt quite a lot, you could probably do it with 21 - using 20
to make a 20-bit counter, which can count up to 1048576, and the last
one to hold the reset pulse for one period of the 1MHz clock. You'd
need quite a bit of combinational logic to persuade the D-types to act
as counters, and some more to initiate the reset pulse at a count of
999,999.
You don't need to decode the 999,999 completely, on an 'up'-only
counter it's sufficient to detect the 1's in the appropriate spots
with a 12-input AND gate. A 74CH74A @5V is fast enough to do a 1MHz
ripple counter with some margin to spare (30ns * 20 = 600ns).
But, I think I'd prefer to do a divide by 15,625 (which only requires
a 6-input AND eg. 74HC11) preceded by a divide-by-32 to give lots of
decode time, and followed by a divide-by-2 to give exactly 50% output
duty cycle @ exactly 1Hz.
theJackal said:Yes . Its been a busy day on Mixer theory here ... LOL
It seems the limit is log10^6/ log12 *4 = 22 flip flops
theJackal said:1)What you're saying is impertinent. First look at the topic ... we
are talking about cascading counters. Look at the denominator
...there is a 12. What does that mean ?
Guess. If you can't ask .
You never seem to understand what I say ...
2)2^20=1,048,576 You won't get 1Mhz with that . You need some more
hardware there-
I've seen some on sale on the webtheJackal wrote:
If you could find a divide-by-12 ic (they have appeared in the
data-books, but I don't recall every seeing one stocked by a
distributor),
you'd still need six of them - 24 bistables.
What it really means is that you weren't thinking straight.
I was acting in a subtle manner, read above ... it wasn't easy forThe real limit is still 20 bistables.
Unfortunately, I understand it all too well - as well as what you don't
say because you haven't understood the problem well enough to think it
through properly.
Regarding the delays I'd measure them before building the circuit. YouThe question was restricted to D-type flip-flops, and I've already
indicated that I'd use one more to produce a tidy reset pulse. ummm
Obviously, you need combinational logic to make such a counter work.
You can use propagation delays through combinational logic to produce a
reset pulse which would be very likely to be wide enough to reset all
the bistables, but since most logic families don't specify minimum
propagation delays, you can't always be absolutely confident of the
reliability of such as system. I've used delay lines to solve this sort
of problem, but they aren't cheap.
By writing log10^6/ log12 *4 = 22 flip flops
I was thinking very straight ... Math stretches right where human
intuition sometimes fails . As I said ask ... and I will explain.
By dividing by log 12 i was getting to the maximum number of mod 12
counters which would be 5. With 5 of those you'd have a frequency of
1000000Hz /2.48832000E+005 =
4.01877572E+000Hz left .
I'd easily handle that with a Mod 4 counter leaving me with
4.01877572E+000Hz/4 = 1.00469393E+000 Hz which is quite good.
Total number of flip flops = 5*4 + 2 = 22 flip flops ... which is what
my simple division of logs up there was saying.
<grin> If I was you I wouldn't bet my life on that ... I got some
ideas on beating that limit!
I was acting in a subtle manner, read above ... it wasn't easy for
anyone to guess where the math was pointing to!
Regarding the delays I'd measure them before building the circuit. You
have at least 4 different types and they can amount to 10's of
nanoseconds which in terms of frequency is a lot . Mostly depend on
the technology of the logic families being used.
Then don't forget clock skews.