Hi, All:
Why PMOS input transistors are usually have lower flicker noise in OPAMP
input pair?
Flicker noise is still not well understood. It is generally believed that
PMOS devices exhibit lower noise because, given n+ poly gates on N and P
devices, the NMOS channel is at the surface of the Si-SiO2 layer, while the
PMOS channel is somewhat below the surface. Since many of the trap points
that lead to flicker noise are at the surface, a buried channel device
should have lower flicker noise.
Recent work [1] has shown that even PMOS devices with surface channels
exhibit lower flicker noise. If this turns out to be true, everything I
said before might not be completely true.
Until confirmation (and a new theory) is available, you probably won't get
in trouble by assuming that a) flicker noise is proportional to the number
of traps in the channel, b) P channel devices have a buried channel that is
physically separated from the Si-SiO2 interface, and c) the number of traps
in the PMOS channel is lower than the number of traps in the NMOS channel.
Here's a question for you to research, Boki: traps produce a Lorentzian
power spectrum (a single pole low pass filter), which is flat at low
frequencies and rolls off at 20dB/decade. Flicker noise has no flat region
and rolls off at 10dB/decade. Why doesn't flicker noise have the same power
spectral density as the traps that create it?
[1] Kenneth K.O., et al., ´1/f Noise of NMOS and PMOS Transistors and
their Implications to Design of Voltage Controlled Oscillators,¡ IEEE
RFIC Symposium, pp. 59-62, 2002.
-- Mike --
