VHDL Generic Coding

[rob_croxford]

Hi All,

I have recently been trying to get into VHDL coding for use on FPGA's. I have been designing an Encoder/Decoder type system for error coding.

I have a question which i hope someone will be able to shed some light on:

I have designed a 7/4 decoder and a 15/11 decoder however i wish to make this code generic in that it the single piece of code will work for both designs.

any help or pointers would be greatly appreciated.

code bellow: (7-4 decoder can also send 15/11 decoder if needed)

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY decoder IS
PORT (clk : IN STD_LOGIC;
res : IN STD_LOGIC;
sin : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(3 downto 0));
END decoder;

ARCHITECTURE behaviour OF decoder IS
SIGNAL control : STD_LOGIC_VECTOR(6 downto 0);
SIGNAL rxlss : STD_LOGIC_VECTOR(3 downto 1);
SIGNAL sipo : STD_LOGIC_VECTOR(6 downto 0);
SIGNAL error : STD_LOGIC_VECTOR(2 downto 0);

BEGIN

error <= sipo(6 downto 4);

PROCESS
BEGIN

WAIT UNTIL RISING_EDGE (clk);

IF(res = '1') THEN
control <= "1000000";
rxlss <= "000";
sipo <= "0000000";

ELSIF(res = '0') THEN
rxlss(1) <= (sin XOR rxlss(3) XOR rxlss(2)) AND NOT(control(0));
rxlss(2) <= rxlss(1) AND NOT(control(0));
rxlss(3) <= rxlss(2) AND NOT(control(0));

sipo <= (sin XOR rxlss(3) XOR rxlss(2)) & sipo(6 downto 1);

IF control(6) = '1' THEN
CASE (error) is
WHEN "001" => dout <= (sipo(3 downto 0)) XOR ("1101");
WHEN "011" => dout <= (sipo(3 downto 0)) XOR ("1010");
WHEN "111" => dout <= (sipo(3 downto 0)) XOR ("0100");
WHEN "110" => dout <= (sipo(3 downto 0)) XOR ("1000");
WHEN OTHERS => dout <= sipo(3 downto 0);
END CASE;
END IF;

control(6 downto 0) <= (control(0)) & (control(6 downto 1));

END IF;
END PROCESS;
END behaviour;

Best regards,

Rob

 

[George_Myers]

Rob,
Ive been working on this for you,
its almost full Generic just the bottom section that needs sorting to do with the error code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;




ENTITY GenDecoder IS
GENERIC ( a : INTEGER := 7;
b : INTEGER := 4);

PORT ( clk : IN STD_LOGIC;
res : IN STD_LOGIC;
sin : IN STD_LOGIC;

dout: OUT STD_LOGIC_VECTOR(a-b downto 0));
END GenDecoder;

ARCHITECTURE behaviour OF GenDecoder IS

SIGNAL control : STD_LOGIC_VECTOR(a-1 downto 0);
SIGNAL rxlss : STD_LOGIC_VECTOR(a-b downto 1);
SIGNAL sipo : STD_LOGIC_VECTOR(a-1 downto 0);
SIGNAL errorcode : STD_LOGIC_VECTOR((a-b)-1 downto 0);


BEGIN

errorcode <= sipo(a-1 downto b);

PROCESS
BEGIN
WAIT UNTIL RISING_EDGE (clk);

IF (res = '1') THEN
control <= std_logic_vector(to_unsigned(2**(a-1), (a)));
rxlss <= std_logic_vector(to_unsigned(0,(a-b)));
sipo <= std_logic_vector(to_unsigned(0,a));


ELSIF (res = '0') THEN

rxlss(1) <= (sin XOR rxlss(3) XOR rxlss(2)) AND NOT(control(0)); --Decoder
rxlss(2) <= rxlss(1) AND NOT(control(0));
rxlss(3) <= rxlss(2) AND NOT (control(0));

sipo <= (sin XOR rxlss(3) XOR rxlss(2)) & sipo((a-1) downto 1); --Serial In Parallel Out

IF control(6)= '1' THEN --Assessor and Corrector
CASE (errorcode) IS
WHEN "001" => dout <= (sipo(a-b downto 0)) XOR ("1101");
WHEN "011" => dout <= (sipo(a-b downto 0)) XOR ("1010");
WHEN "111" => dout <= (sipo(a-b downto 0)) XOR ("0100");
WHEN "110" => dout <= (sipo(a-b downto 0)) XOR ("1000");
WHEN OTHERS => dout <= sipo(a-b downto 0);
END CASE;
END IF;

control(a-1 downto 0) <= (control(0))& (control(a-1 downto 1));

END IF;
END PROCESS;
END behaviour;


if you have any ideas about the rest it would be good to know

Regards
George